Results 131 to 140 of about 1,145 (180)

Kilo-core Wireless Network-on-Chips (NoCs) Architectures

Proceedings of the Second Annual International Conference on Nanoscale Computing and Communication, 2015
As energy-efficiency and high-performance of Networks-on-Chips (NoCs) communication fabric have become critical, limited bandwidth and fundamental signaling limitations of metallic interconnects have forced academia and industry to consider emerging technologies such as wireless interconnects as an alternate solution.
Avinash Karanth Kodi, Md. Ashif I. Sikder, Dominic DiTomaso, Savas Kaya, Soumyasanta Laha, David W. Matolak, William Rayess   +6 more
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Special Section on International Symposium on Networks-on-Chip (NOCS)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009
The idea for this special section started with the intention to archive the top papers from the First ACM/IEEE International Symposium on Networks on Chips (NOCS) in 2007. The first two papers tackle the tight power constraints of on-chip network design.
Avinoam Kolodny, Li-Shiuan Peh
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RAP-NoC

Proceedings of the Eight Annual ACM International Conference on Nanoscale Computing and Communication, 2021
Nowadays, optical network-on-chip is accepted as a promising alternative solution for traditional electrical interconnects due to lower transmission delay and power consumption as well as considerable high data bandwidth. However, silicon photonics struggles with some particular challenges that threaten the reliability of the data transmission process.
Meisam Abdollahi, Mohammad Baharloo, Fateme Shokouhinia, Masoumeh Ebrahimi   +3 more
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ON DESIGN AND APPLICATION MAPPING OF A NETWORK-ON-CHIP(NOC) ARCHITECTURE

Parallel Processing Letters, 2008
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either traditional or multi-layer bus architectures because of their poor scalability and bandwidth limitation on a single bus.
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungsook Yang, Nader Bagherzadeh   +4 more
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Virtual Channels in Networks on Chip: Implementation and Evaluation on Hermes NoC

2005 18th Symposium on Integrated Circuits and Systems Design, 2005
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congestion in NoCs reduces the overall system performance. This effect is particularly strong in networks where a single buffer is associated with each input channel, which simplifies
Aline Mello 0001, Leonel Tedesco, Ney Calazans, Fernando Moraes 0001   +3 more
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Benchmarking Network-on-Chip (NoC) Designs

2012
This chapter describes the basics of benchmarking a Network-on-chip (NoC) that interconnects resources in a complex integrated circuit. Common NoC benchmarks and disciplined methodology are needed to compare NoC proposals in fair manner and they also help other researchers to repeat the published experiments.
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Clustered NOC, a suitable design for group communications in Network on Chip

Computers & Electrical Engineering, 2012
In this paper, a Clustered NOC (C-NOC) is introduced to improve the performance of Hermes-NOC (H-NOC) in group communication. Each C-NOC switch has eight bi-directional ports connected to four neighbor switches and four local ports. With the same (IP) cores in both H-NOC and C-NOC networks, the ordinal size of C-NOC is 75% less than H-NOC. In corner-to-
Mohammad Reza Seifi, Mohammad Eshghi
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R-NoC: An Efficient Packet-Switched Reconfigurable Networks-on-Chip

2012
Networks-on-Chip (NoC) architectures have been proposed to replace the classical bus and point-to-point global interconnections for the next generation of multiple-core systems-on-a-chips. However, the one-to-one (unicast) based NoC communication paradigm is not efficient for one-to-many (multicast) communication requests, and the address based packet ...
Hongbing Fan, Yue-Ang Chen, Yu-Liang Wu
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A variable frequency link for a power-aware network-on-chip (NoC)

Integration, 2009
Although the technology scaling has enabled designers to integrate a large number of processors onto a single chip realizing chip multi-processor (CMP), problems arising from technology scaling have made power reduction an important design issue. Since interconnection networks dissipate a significant portion of the total system power budget, it is ...
Seung Eun Lee, Nader Bagherzadeh
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Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip

2005
Traditionally, the design of on-chip interconnects has been an afterthought in the design process of integrated circuits. As the complexity of interconnect and the capacitance, inductance and resistance associated with the wires have increased with technology scaling, the delays associated with wires can no longer be neglected.
Theocharis Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin   +3 more
openaire   +1 more source