Results 151 to 160 of about 11,736 (210)

A Reinforcement Learning Based Approach for Efficient Routing in Multi-FPGA Platforms. [PDF]

Sensors (Basel)
Farooq U, Mehrez H, Hasan NU.
europepmc   +1 more source

Spike-based dynamic computing with asynchronous sensing-computing neuromorphic chip. [PDF]

Nat Commun
Yao M, Richter O, Zhao G, Qiao N, Xing Y, Wang D, Hu T, Fang W, Demirci T, De Marchi M, Deng L, Yan T, Nielsen C, Sheik S, Wu C, Tian Y, Xu B, Li G.   +17 more
europepmc   +1 more source

Polysaccharide from Walnut Green Husk alleviates ochratoxin a-induced anorexia in chicks via m⁶A-mediated FXR regulation of orexigenic genes. [PDF]

Poult Sci
Zhao K, Hu J, Jiang L, Zhao R, Wang D, Yang Y.   +5 more
europepmc   +1 more source

ceRNA regulatory network and immune-neurodegenerative mechanisms of peripheral CD4+ T cells in parkinson's disease. [PDF]

PLoS One
Guo L, Li Q, Li J, Yang F.
europepmc   +1 more source

DNA Transactions in Bacteria and Membranes: A Place for the Hfq Protein? [PDF]

Membranes (Basel)
Bloch S, Sinden RR, Wien F, Węgrzyn G, Arluison V.   +4 more
europepmc   +1 more source

Design and Modeling of a Terahertz Transceiver for Intra- and Inter-Chip Communications in Wireless Network-on-Chip Architectures. [PDF]

Sensors (Basel)
Paudel B, Li XJ, Seet BC.
europepmc   +1 more source

Advancements in cache management: a review of machine learning innovations for enhanced performance and security. [PDF]

Front Artif Intell
Krishna K.
europepmc   +1 more source

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A high level power model for Network-on-Chip (NoC) router

Computers & Electrical Engineering, 2009
This paper presents a high level power estimation methodology for a Network-on-Chip (NoC) router, that is capable of providing cycle accurate power profile to enable power exploration at system level. Our power macro model is based on the number of flits passing through a router as the unit of abstraction. Experimental results show that our power macro
Seung Eun Lee, Nader Bagherzadeh
openaire   +3 more sources

Versal Network-on-Chip (NoC)

2019 IEEE Symposium on High-Performance Interconnects (HOTI), 2019
Xilinx Versal Adaptable Compute Acceleration Platform (ACAP) is a new software-programmable heterogenous compute platform. The slowing of Moores law and the everpresent need for higher levels of compute performance has spurred the development of many domain specific accelerator architectures. ACAP devices are well suited to take advantage of this trend.
Ian Swarbrick, Dinesh Gaitonde, Sagheer Ahmad, Bala Jayadev, Jeff Cuppett, Abbas Morshed, Brian Gaide, Ygal Arbel   +7 more
openaire   +1 more source

UTAR NoC: Adaptive Network on Chip architecture platform

2015 3rd International Conference on New Media (CONMEDIA), 2015
Network-on-Chip (NoC) has been proposed as a solution for the communication challenges of Multi-Processor System-on-chip (MPSoC) design in nanoscale technologies and it has better reusability and scalability. However along with the advantages of any communication parameter follow its disadvantages.
Felix Lokananta, S. W. Lee, M. S. Ng, Z. N. Lim, C. M. Tang   +4 more
openaire   +1 more source