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Network-On-Chip (NoC) - Routing Techniques: A Study and Analysis
2019 Global Conference for Advancement in Technology (GCAT), 2019NoC is a communication system that applies networking concepts to On-chip Communication and it provides advantages over Common bus architectures. As VLSI technology progressed diverse, powerful SoCs became viable. In this paper a comparative analysis of the different routing techniques in NoC is discussed.
Uma R, Sarojadevi H., Sanju V.
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Benchmarking Network-on-Chip (NoC) Designs
2012This chapter describes the basics of benchmarking a Network-on-chip (NoC) that interconnects resources in a complex integrated circuit. Common NoC benchmarks and disciplined methodology are needed to compare NoC proposals in fair manner and they also help other researchers to repeat the published experiments.
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Special Section on International Symposium on Networks-on-Chip (NOCS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009The idea for this special section started with the intention to archive the top papers from the First ACM/IEEE International Symposium on Networks on Chips (NOCS) in 2007. The first two papers tackle the tight power constraints of on-chip network design.
Avinoam Kolodny, Li-Shiuan Peh
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Cloud-based evolutionary algorithm for Network on Chip (NoC) test scheduling using NoC as TAMs
SPIE Proceedings, 2013Network on Chip is a novel system-on-chip paradigm. Developing an efficient test strategy is essential for future NoC development. We propose to use cloud theory to solve core test scheduling problem for NoC using NoC communication network as test access mechanisms (TAMs).
Chuanpei Xu +3 more
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Virtual Channels in Networks on Chip: Implementation and Evaluation on Hermes NoC
2005 18th Symposium on Integrated Circuits and Systems Design, 2005Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congestion in NoCs reduces the overall system performance. This effect is particularly strong in networks where a single buffer is associated with each input channel, which simplifies
Aline Mello +3 more
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R-NoC: An Efficient Packet-Switched Reconfigurable Networks-on-Chip
2012Networks-on-Chip (NoC) architectures have been proposed to replace the classical bus and point-to-point global interconnections for the next generation of multiple-core systems-on-a-chips. However, the one-to-one (unicast) based NoC communication paradigm is not efficient for one-to-many (multicast) communication requests, and the address based packet ...
Hongbing Fan, Yue-Ang Chen, Yu-Liang Wu
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Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip
2005Traditionally, the design of on-chip interconnects has been an afterthought in the design process of integrated circuits. As the complexity of interconnect and the capacitance, inductance and resistance associated with the wires have increased with technology scaling, the delays associated with wires can no longer be neglected.
Theocharis Theocharides +3 more
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Asynchronous network-on-chips (NoCs) for resource efficient many core architectures
2019In this chapter, different GALS approaches for the implementation of embedded NoC architectures were presented. The GALS approach allows for the reduction of the resource requirements at an increased scalability of the NoC without sacrificing performance. The three approaches of synchronous, mesochronous, and asynchronous NoCs were compared.
Ax, Johannes +6 more
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Special Issue on Network-on-Chips (NoCs)
Journal of Parallel and Distributed Computing, 2010Ahmed Louri, Avinash Kodi
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