Results 161 to 170 of about 11,736 (210)

Interconnect intellectual property for Network-on-Chip (NoC)

Journal of Systems Architecture, 2004
As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a Network-on-Chip (NoC) architecture was proposed by different authors [Route packets, not wires: on-chip interconnection networks, in: Design Automation ...
Jian Liu, Li-Rong Zheng, Hannu Tenhunen
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Kilo-core Wireless Network-on-Chips (NoCs) Architectures

Proceedings of the Second Annual International Conference on Nanoscale Computing and Communication, 2015
As energy-efficiency and high-performance of Networks-on-Chips (NoCs) communication fabric have become critical, limited bandwidth and fundamental signaling limitations of metallic interconnects have forced academia and industry to consider emerging technologies such as wireless interconnects as an alternate solution.
Avinash K. Kodi, Md Ashif I. Sikder, Dominic DiTomaso, Savas Kaya, Soumyasanta Laha, David Matolak, William Rayess   +6 more
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Networks-on-Chip (NoC)

2011
The move to many-core system is expected to become the dominant trend in the near future. With technology scaling into nanoscale regime, hundreds and even thousands of intellectual property (IP) cores can be integrated into a single chip. How to provide efficient and reliable communication between these IP cores becomes a bit problem.
Bo Fu, Paul Ampadu
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Efficient 2DMesh Network on Chip (NoC) Considering GALS Approach

2009 Fourth International Conference on Computer Sciences and Convergence Information Technology, 2009
State of the art VLSI systems are characterised by their small, deca-nano feature size. In order to accommodate the complexity and scalability, a new design paradigm, System on Chip (SoC) has been introduced. Performance and power of giga-scale SoC is ever more communication-dominated.
Mohammed Anis Ur Rahman, Imtiaj Ahmed, Fernando Rodriguez, Naimul Islam   +3 more
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Secure Model Checkers for Network-on-Chip (NoC) Architectures

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
As chip multiprocessors (CMPs) are becoming more susceptible to process variation, crosstalk, and hard and soft errors, emerging threats from rogue employees in a compromised foundry are creating new vulnerabilities that could undermine the integrity of our chips with malicious alterations.
Travis Boraten, Dominic DiTomaso, Avinash Karanth Kodi   +2 more
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3D(Dimensional)—Wired and Wireless Network-on-Chip (NoC)

2020
Network on Chip is a special unique case of parallel computing systems defined by the tight constraints such as availability of resources, area, cost of the NoC architecture and power consumption. NoC is designed with three main components: switches, Network Interfaces (NIs) and links.
N. Ashokkumar, P. Nagarajan, P. Venkatramana   +2 more
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Efficient Network on Chip (NoC) using heterogeneous circuit switched routers

2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA), 2016
Network-on-Chip (NoC) architecture in recent years has been considered as the overwhelming communication solution to provide scalability in multi core systems over traditional bus-based communication architecture. There is an increased use of multi-core with NoC in embedded systems solutions. Energy efficiency in the Network-on-Chip (NoC) is one of the
Anuja Naik, Tirumale K. Ramesh
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Design Challenges for 3 Dimensional Network-on-Chip (NoC)

2019
NoC (Network-on-Chip) is a technology is expected for resolve the problem of short imminence of buses. This technology approach is to design the information exchange between the subsystem of IP cores. The usage of common buses, which have the problem that they cannot scale in concern fixed and also the number of resources grows.
N. AshokKumar, P. Nagarajan, SathishKumar Selvaperumal, P. Venkatramana   +3 more
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Performance evaluation of three Network-on-Chip (NoC) architectures (Invited)

2012 1st IEEE International Conference on Communications in China (ICCC), 2012
As the number of processing elements which can be placed on a single chip doubles about every two years, both System-on-Chip (SoC) and the microprocessor market call for high-performance, flexible, scalable, and design-friendly interconnection network architectures [1].
Jie Chen, Paul Gillard, Cheng Li
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Bufferless NoC router design for optical networks-on-chip

Journal of Optical Communications
Abstract In large-scale tiled chip multiprocessors (TCMPs), network-on-chip (NoC) is a prevalent interconnect solution. The NoC router plays a crucial role in NoC architecture, and two primary types exist: buffered and bufferless. The latter offers a promising solution due to its streamlined design, reduced energy consumption, and ...
Ramanamma Parepalli, Sanjeev Shama, Mohan Kumar Naik   +2 more
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