A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016Paul Bogdan +2 more
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Secured Network on Chip (NoC) Architecture and Routing with Modified TACIT Cryptographic Technique
Procedia Computer Science, 2015Adesh Kumar +2 more
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Mathematical formalisms for performance evaluation of networks-on-chip
ACM Computing Surveys, 2013Axel Jantsch, Zhonghai Lu
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Codesign of NoC and Cache Organization for Reducing Access Latency in Chip Multiprocessors
IEEE Transactions on Parallel and Distributed Systems, 2012Ahmed Abousamra, Rami Melhem
exaly
Congestion-aware core mapping for Network-on-Chip based systems using betweenness centrality
Future Generation Computer Systems, 2018Tahir Maqsood +2 more
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Enabling High-Performance SMART NoC Architectures Using On-Chip Wireless Links
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017Karthi Duraisamy, Partha Pande
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Proffering Secure Energy Aware Network-On-Chip (Noc) Using Incremental Cryptogine
Sustainable Computing: Informatics and Systems, 2022exaly
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016Yao Chen, Yun Liang, Kyle Rupnow
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Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines
Journal of Parallel and Distributed Computing, 2019Dipika Deb, John Jose, Shirshendu Das
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