Results 81 to 90 of about 124,522 (260)
A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation
Wireless communication at near-capacity transmission throughputs is facilitated by employing sophisticated Error Correction Codes (ECCs), such as turbo codes.
Ra'ed Al-Dujaily +5 more
doaj +1 more source
Design of GPU Network-on-Chip for Real-Time Video Super-Resolution Reconstruction. [PDF]
Peng Z, Du J, Qiao Y.
europepmc +1 more source
Optimization of the Production of Rubber Compounds Using Mathematical Models
Rubber compounds were mixed in a batch internal mixer, and symbolic regression was used to derive mathematical models linking recipe and process parameters to ram path, torque, and mixing quality (incorporation, dispersion, distribution). Subsequent optimization with evolutionary algorithms identified operating conditions that reduce specific energy ...
Anke Bardehle +7 more
wiley +1 more source
In the paradigm of Device-to-Device (D2D) and System-on-Chip (SoC) communications, the optimization of high-speed data transfer while minimizing hardware resource utilization imposing paramount importance. Traditional methodologies have often resulted in
P. Anuradha +9 more
doaj +1 more source
MRONoC: A Low Latency and Energy Efficient on Chip Optical Interconnect Architecture
The circuit switched optical network on chip (ONoC) is popularly employed since the optical buffer is not available. However, this technique suffers from limited transmission bandwidth, high setup-time overhead, and high network resource contention ...
Huaxi Gu +4 more
doaj +1 more source
Modular Critical Element Recycling Platform Using a Nanoporous Additively Manufactured Gyroid
A modular recycling platform integrates 3D‐printed nanoporous gyroid structures to enable efficient critical element recovery. This system utilizes a hierarchical architecture, combining macroscopic channels with polymerization‐induced nanoscale porosity. By systematically tuning structural wall thickness and resin formulation, the platform achieves an
Xiangyu Gao +6 more
wiley +1 more source
Performance analysis of multiple input single layer neural network hardware chip. [PDF]
Goel A, Goel AK, Kumar A.
europepmc +1 more source
An all‐in‐one analog AI accelerator is presented, enabling on‐chip training, weight retention, and long‐term inference acceleration. It leverages a BEOL‐integrated CMO/HfOx ReRAM array with low‐voltage operation (<1.5 V), multi‐bit capability over 32 states, low programming noise (10 nS), and near‐ideal weight transfer.
Donato Francesco Falcone +11 more
wiley +1 more source
TTQR: A Traffic- and Thermal-Aware Q-Routing for 3D Network-on-Chip. [PDF]
Liu H, Chen X, Zhao Y, Li C, Lu J.
europepmc +1 more source
From Food to Power: Hydrogel Thermoelectrics for Ingestible Electronics
We introduce a fully edible thermoelectric–electrochromic platform that harvests heat from food and converts it into a visible color change. N‐type and p‐type hydrogel thermoelectric generators connected in series power anthocyanin‐based electrochromic displays, demonstrating the feasibility of safe, biodegradable, ingestible systems for on‐food ...
Antonia Georgopoulou +3 more
wiley +1 more source

