Results 21 to 30 of about 31,431,766 (171)
A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs [PDF]
, 2006 Among the different types of algorithms proposed to test static random access memories (SRAMs), march tests have proven to be faster, simpler and regularly structured.
Di Natale, Giorgio +4 more
core +1 more source
March Test Generation Revealed [PDF]
, 2008 Memory testing commonly faces two issues: the characterization of detailed and realistic fault models and the definition of time-efficient test algorithms.
Di Natale, Giorgio +5 more
core +1 more source
The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET
Nanoscale Research Letters, 2017 The larger volume of capacitor and higher leakage current of transistor have become the inherent disadvantages for the traditional one transistor (1T)-one capacitor (1C) dynamic random access memory (DRAM).
Wei Li +4 more
doaj +1 more source
Hybrid flexible resistive random access memory-gated transistor for novel nonvolatile data storage
, 2016 Here, a single‐device demonstration of novel hybrid architecture is reported to achieve programmable transistor nodes which have analogies to flash memory by incorporating a resistive switching random access memory (RRAM) device as a resistive switch ...
Sun, Qijun +9 more
core +1 more source
Current-Mode Readout of Dynamic Random-Access Memories [PDF]
Port Said Engineering Research Journal, 2012 During the reading of one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) cells, the need arises to amplify a small voltage difference (in the order of 30 to 100 mV) by a suitable sense amplifier.
doaj +1 more source
Hyperparallel transistor, router and dynamic random access memory with unity fidelities
, 2021 We theoretically implement some hyperparallel optical elements, including quantum single photon transistor, router, and dynamic random access memory (DRAM).
Ming Hua (1877884) +4 more
core +1 more source
Benchmarking of FERAM-Based Memory System by Optimizing Ferroelectric Device Model
IEEE Journal on Exploratory Solid-State Computational Devices and CircuitsWe present a framework for design technology co-optimization (DTCO) of the main memory system with one transistor-one capacitor (1T1C) ferroelectric random access memory (FERAM) as an alternative to dynamic random access memory (DRAM).
Mohammad Adnaan +6 more
doaj +1 more source
A New Electron Bridge Channel 1T-DRAM Employing Underlap Region Charge Storage
IEEE Journal of the Electron Devices Society, 2017 We experimentally demonstrate a new type of silicon-based capacitorless one-transistor dynamic random access memory (1T-DRAM) with an electron-bridge channel. The fabrication steps are fully compatible with modern CMOS technology.
Jyi-Tsong Lin +5 more
doaj +1 more source
Advanced Functional Materials, EarlyView.In MOCVD MoS2 memristors, a current compliance‐regulated Ag filament mechanism is revealed. The filament ruptures spontaneously during volatile switching, while subsequent growth proceeds vertically through the MoS2 layers and then laterally along the van der Waals gaps during nonvolatile switching.
Yuan Fa +19 more
wiley +1 more source
Advanced Functional Materials, EarlyView.Optoelectronic synaptic devices based on solution‐processed molecular telluride GST‐225 phase‐change inks are demonstrated for three‐factor learning. A global optical signal broadcast through a silicon waveguide induces non‐volatile conductance updates exclusively in locally electrically flagged memristors.
Kevin Portner +14 more
wiley +1 more source