Results 11 to 20 of about 19,689 (303)
IEEE Access, 2022 A novel modeling methodology is developed for interconnect parasitic capacitances in rule-based extraction tools. Traditional rule-based extraction tools rely on pattern matching operations to match every interconnect structure with corresponding pre ...
Mohamed Saleh Abouelyazid +2 more
doaj +3 more sources
Nonlinear Parasitic Capacitance Modelling of High Voltage Power MOSFETs in Partial SOI Process [PDF]
, 2016 State-of-the-art power converter topologies such as resonant converters are either designed with or affected by the parasitic capacitances of the power switches.
Fan, Lin +2 more
core +2 more sources
The consequences of the application of a floating gate on d.c.-MISFET characteristics [PDF]
, 1984 In the literature the influence of the conducting layer, sometimes called a floating gate, upon d.c.-MISFET characteristics is ignored or only treated in a phenomenological way. Our intentions in this paper are to present a study of the consequences of a
Bergveld, P., Voorthuyzen, J.A.
core +12 more sources
Sensors, 2012 Series-connected thin film piezoelectric elements can generate large output voltages. The output voltage ideally is proportional to the number of connections.
Kensuke Kanda +4 more
doaj +1 more source
Analysis of the Zero Overvoltage Switching Phenomenon
IEEE Access, 2022 In common understanding, the fast switching speed of wide-bandgap devices leads to high overvoltage and oscillations, if no countermeasures are taken. Those countermeasures were introduced in the past, and include methods such as build-in gate resistors ...
Nico Schmied, Stefan Matlok, Martin Marz
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50-nm self-aligned and 'standard' T-gate InP pHEMT comparison: the influence of parasitics on performance at the 50-nm node [PDF]
, 2006 Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date.
Elgaid, K. +5 more
core +1 more source
A comprehensive design approach for a three‐winding planar transformer
IET Power Electronics, 2022 In this paper, a new three‐winding planar transformer design with the integrated leakage inductor is proposed for a triple‐active‐bridge converter. It enables two output voltage levels: a high voltage (HV) output port and a low voltage (LV) output port ...
Shenli Zou +3 more
doaj +1 more source
Calculation Model of Parasitic Capacitance for High-Frequency Inductors and Transformers
IEEE Access, 2023 With high power density and high-frequency power electronics technologies, parasitic capacitances of inductors and transformers have been widely discussed, in which parasitic capacitance may lead to electromagnetic interference (EMI) and efficiency ...
Yujie Lan +4 more
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Parasitic capacitance cancellation in filter inductors [PDF]
2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551), 2004 This paper introduces a technique for improving the high-frequency performance of filter inductors and common-mode chokes by cancelling out the effects of parasitic capacitance. This technique uses additional passive components to inject a compensation current that cancels the parasitic current, thereby improving high-frequency filtering performance ...
Neugebauer, Timothy C. +1 more
openaire +2 more sources
Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits [PDF]
, 2009 We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs).
Delgado Restituto, Manuel +2 more
core +1 more source