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Simultaneously Estimating Process Variation Effect, Work Function Fluctuation, and Random Dopant Fluctuation of Gate-All-Around Silicon Nanosheet Complementary Field-Effect Transistors. [PDF]
Kola SR, Li Y.
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Switching Loss Model for SiC MOSFETs Based on Datasheet Parameters Enabling Virtual Junction Temperature Estimation. [PDF]
Bianchini C +3 more
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Numerical Investigation on Electrothermal Performance of AlGaN/GaN HEMTs with Nanocrystalline Diamond/SiNx Trench Dual-Passivation Layers. [PDF]
Wang P +9 more
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Development of a 3D capacitive gyroscope with reduced parasitic capacitance
Journal of Micromechanics and Microengineering, 2013We present the development of a technological platform dedicated to 3D capacitive inertial sensors. The proof of concept will be made on a 3D gyroscope. The mobile structure is made within a 30 µm thick Si top layer of a SOI substrate, while poly-Si deposited on top of a sacrificial PSG layer serves as suspended top electrodes and connection wires ...
A Walther +5 more
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Efficient extraction of metal parasitic capacitances
Proceedings International Conference on Microelectronic Test Structures, 2002Accurate extraction of parasitic capacitances associated with fine pitch metallisation layers is essential in the design of ULSI ICs. This paper reports on investigation of the impact of test structure design on extracted values for inter-layer and intra-layer capacitances; the influence of topography is also reviewed.
G.J. Gaston, I.G. Daniels
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Parasitic capacitance effects of planar resistors
IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1989The intrinsic capacitance of a planar resistor in a hybrid circuit is discussed. Basic theory is outlined to model the self-capacitance effect of resistive layers. A perturbation method is derived where the zeroth order accounts for the pure resistive effects and the first-order perturbation deals with the capacitive effects.
S.N. Demurie, G. De Mey
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