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2006 43rd ACM/IEEE Design Automation Conference, 2006
Power gating is effective for reducing leakage power. Previously, a distributed sleep transistor network (DSTN) was proposed to reduce the sleep transistor area by connecting all the virtual ground lines together to minimize the maximum instantaneous current (MIC) through sleep transistors.
De-Shiuan Chiou +3 more
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Power gating is effective for reducing leakage power. Previously, a distributed sleep transistor network (DSTN) was proposed to reduce the sleep transistor area by connecting all the virtual ground lines together to minimize the maximum instantaneous current (MIC) through sleep transistors.
De-Shiuan Chiou +3 more
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Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG)
2013Leakage and switching power of circuit can be minimised in FSM based power gating technique by partitioning and encoding of FSM.Depending on the state of machine, at a time one sub-FSM is in power gated mode, but other one is in active mode which continues to dissipate power.In active sub-FSM, it is possible to reduce leakage, if the clock period is ...
Debanjali Nath +2 more
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Power Optimization Using Clock Gating and Power Gating
2016The scaling of CMOS technology has continued due to ever increasing demand of greater performance with low power consumption. This demand has grown further by the portable and battery operated devices market. To meet the challenge of greater energy efficiency and performance, a number of power optimization techniques at processor and system components ...
Arsalan Shahid +3 more
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Power-Gating Aware Floorplanning
8th International Symposium on Quality Electronic Design (ISQED'07), 2007Power-gating is a technique for efficiently reducing leakage power by shutting off the idle blocks. However, the presence of power-gating may also introduce negative effects, which are not considered in the earlier design stages. Ignoring those effects may result in suboptimal designs and potentially even nullify the intended power savings.
Hailin Jiang, Malgorzata Marek-Sadowska
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, 2008 Clock gating and power gating are two of the most effective techniques that are applied today for reducing dynamic and leakage power, respectively, in digital CMOS circuits.
Andrea Calimera +2 more
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Control for Power Gating of Wires
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010In the deep sub-micron domain wires consume more power than transistors. Power Gating for Wires is a form of bus segmentation that alleviates the power loss from on-chip interconnects, by switching off the supply voltage from inactive drivers, cycle by instruction-cycle.
Kris Heyrman +4 more
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Proceedings of the 48th Design Automation Conference, 2011
Power gating is essential for controlling leakage power dissipation of modern chip designs. However, power gating introduces unique power delivery integrity issues and tradeoffs between switching and rush current (wake-up) supply noises. In addition, in power-gated power delivery networks (PDNs), the amount of power saving intrinsically trades off with
Tong Xu 0004, Peng Li 0001, Boyuan Yan
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Power gating is essential for controlling leakage power dissipation of modern chip designs. However, power gating introduces unique power delivery integrity issues and tradeoffs between switching and rush current (wake-up) supply noises. In addition, in power-gated power delivery networks (PDNs), the amount of power saving intrinsically trades off with
Tong Xu 0004, Peng Li 0001, Boyuan Yan
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A note on the power of majority gates and modular gates
Information Processing Letters, 1995zbMATH Open Web Interface contents unavailable due to conflicting licenses.
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GATE RESIZING TO REDUCE POWER CONSUMPTION
International Journal of Foundations of Computer Science, 2002We study the problem of resizing gates so as to reduce overall power consumption while satisfying a circuit's timing constraints. Polynomial time algorithms for series-parallel and tree circuits are obtained. Gate resizing with multigate modules is shown to be NP-hard.
Edward Y. C. Cheng, Sartaj Sahni
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On the power of a threshold gate at the top
Information Processing Letters, 1997zbMATH Open Web Interface contents unavailable due to conflicting licenses.
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