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Power-Clock Gating

2012
A very efficient and easy to implement method to cut down energy losses in idle times is proposed, the so-called power-clock gating. The basic idea is to use a switch to disconnect the power-clock from the adiabatic circuit when no operations are performed in the system. The theory to power-clock gating is presented and figures are derived to allow for
openaire   +1 more source

Analysis and optimization of power-gated ICs with multiple power gating configurations

2007 IEEE/ACM International Conference on Computer-Aided Design, 2007
Aida Todri   +2 more
openaire   +1 more source

Salvaging Gate-Drive Power in Switched Power Supplies

2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), 2023
Guillaume Guérin   +1 more
openaire   +1 more source

Dynamic power-gating for leakage power reduction in FPGAs

Frontiers of Information Technology & Electronic Engineering, 2023
openaire   +2 more sources

A 24.9% Power Reduction Active Gate Driver With Power Gating and Current Modulation for Power MOSFETs

IEEE Transactions on Circuits and Systems II: Express Briefs
Chua-Chin Wang   +6 more
openaire   +2 more sources

Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating

IEEE Transactions on Circuits and Systems II: Express Briefs, 2020
José G Delgado-Frias, Michael Turi
exaly  

Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007
Dennis Sylvester
exaly  

Efficient Partial Scan Cell Gating for Low-Power Scan-Based Testing

ACM Transactions on Design Automation of Electronic Systems, 2009
Chrysovalantis Kavousianos   +2 more
exaly  

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