Results 251 to 260 of about 5,609,086 (296)

Warped gates

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
With the widespread adoption of GPGPUs in varied application domains, new opportunities open up to improve GPGPU energy efficiency. Due to inherent application-level inefficiencies, GPGPU execution units experience significant idle time. In this work we propose to power gate idle execution units to eliminate leakage power, which is becoming a ...
Mohammad Abdel-Majeed, Daniel Wong 0001, Murali Annavaram   +2 more
openaire   +1 more source

Overdrive Power-Gating Techniques for Total Power Minimization

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007
We investigate how to apply power-gating techniques to logic circuits for maximal total power reduction. We compare techniques that employ overdriven low-Vt power switches (SCCMOS) with those employing high-Vt power switches (MTCMOS). When sized under the same constraints for maximum voltage drop in active mode, MTCMOS has 10% shorter total wake-up ...
Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson   +2 more
openaire   +1 more source

Generic Power at the Gate

World Englishes, 1997
Generic power is the ability to anticipate elements in a predictable sequence in a communicative event. This paper examines the role of such power in a crucial situation, namely the admission interview in the Republic of Singapore. In such a strategic occasion, both the interviewer (IR) and the interviewee (IE) are strictly constrained by generic ...
openaire   +1 more source

Adaptive Power Control Technique on Power-Gated Circuitries

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011
An adaptive power control (APC) system on power-gated circuitries is proposed. The core technique is a switching state determination mechanism as an alternative of critical path replicas. It is intrinsically tolerant of process, voltage, and temperature (PVT) variations because it directly monitors the behavior of VDDV node.
Wei-Chih Hsieh, Wei Hwang
openaire   +1 more source

Efficient checking of power delivery integrity for power gating

2011 12th International Symposium on Quality Electronic Design, 2011
Multi-core architecture has emerged as the primary architectural choice to achieve power-efficient computing in microprocessors and SoCs. Power gating is indispensable for system power and thermal management and well suited for multi-core architectures.
Zhiyu Zeng, Zhuo Feng, Peng Li 0001
openaire   +2 more sources

Power gating scheduling for power/ground noise reduction

Proceedings of the 45th annual Design Automation Conference, 2008
Power gating is a technique for efficiently reducing leakage power by disconnecting idle blocks from the power grid. When gated blocks are woken up, large amounts of switching currents are drawn in a short period of time that may introduce severe noise on the power delivery mesh.
Hailin Jiang, Malgorzata Marek-Sadowska
openaire   +2 more sources

The power of the school gate

SecEd, 2018
Facing problems with pupils arriving in class not prepared for learning, and the disruption this causes, school leader Allen Hall drew a red line at the school gate in a bid to change habits and ensure pupils arrived at school ready for the day ahead
openaire   +1 more source

Benefits and costs of power-gating technique

2005 International Conference on Computer Design, 2006
Power-gating is a technique for saving leakage power by shutting off the idle blocks. However, without good understanding and careful design, negative effects of power gating may overwhelm the potential gain and may make the technique not worth the effort.
Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif   +2 more
openaire   +2 more sources

Power gating in wireless sensor networks

2008 3rd International Symposium on Wireless Pervasive Computing, 2008
In this paper we investigate power-saving techniques that employ the on-chip power gating to reduce the static power loss. Gating the power of single functional blocks in a wireless sensor node with help of a power management unit and power gates, we minimize the static power loss in a wireless sensor network.
Goran Panic, Zoran Stamenkovic, Rolf Kraemer   +2 more
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Innovative power gating for leakage reduction

2008 IEEE International Symposium on Circuits and Systems, 2008
Leakage has become one of the most dominant factors of power management and signal integrity of nanometer scale integrated circuits. Recently, power gating structures has proven to be effective in controlling leakage. In this paper an alternative dual-F/A reduced power gating structure is proposed for better reduction of leakage currents, especially ...
Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled   +2 more
openaire   +2 more sources