Results 261 to 270 of about 207,528 (316)
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Processor Scheduling for Linearly Connected Parallel Processors
IEEE Transactions on Computers, 1986Summary: A low-level parallel processor (LLPP) is one in which two or more machine-level operations are executed in parallel. This paper analyzes the use of linearly connected LLPP's for parallel evaluation of program fragments. A graph-theoretic model is presented which describes the communication constraints of linearly connected parallel processors.
Charles E. McDowell, William F. Appelbe
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Proceedings of the 41st annual Design Automation Conference, 2004
We describe a new processing architecture, known as a warp processor, that utilizes a field-programmable gate array (FPGA) to improve the speed and energy consumption of a software binary executing on a microprocessor. Unlike previous approaches that also improve software using an FPGA but do so using a special compiler, a warp processor achieves these
Roman L. Lysecky +2 more
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We describe a new processing architecture, known as a warp processor, that utilizes a field-programmable gate array (FPGA) to improve the speed and energy consumption of a software binary executing on a microprocessor. Unlike previous approaches that also improve software using an FPGA but do so using a special compiler, a warp processor achieves these
Roman L. Lysecky +2 more
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Processor-processor communication
Microprocessors and Microsystems, 1979Abstract Loosely coupled distributed microcomputer systems require communication links between different computer configurations. Byte oriented serial links provide a simple way of overcoming the problems of incompability between the computer configurations. The communications protocol, hardware and software for handling such links are discussed.
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Proceedings of COMPCON '94, 2002
The IBM POWER2 is a second-generation, multi-chip superscalar RISC processor. It provides dual branch processing units, dual fixed-point units, dual floating-point units, and advanced superscalar techniques. It is capable of executing 6 instructions per cycle and 8 operations per cycle.
Jama Barreh +3 more
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The IBM POWER2 is a second-generation, multi-chip superscalar RISC processor. It provides dual branch processing units, dual fixed-point units, dual floating-point units, and advanced superscalar techniques. It is capable of executing 6 instructions per cycle and 8 operations per cycle.
Jama Barreh +3 more
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Processor-Centric Design: Processors, Multi-Processors, and Software
2009Almost all embedded systems are a combination of software running on embedded processor cores, supporting hardware such as memories and processor buses, and other hardware elements including function accelerators and peripheral interface blocks. As a result, systems design increasingly is taking a processor-centric focus.
Brian Bailey, Grant Martin
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Proceedings of the October 27-29, 1964, fall joint computer conference, part I on XX - AFIPS '64 (Fall, part I), 1964
This paper describes the computer system designed under an Air Force sponsored study program to develop a non-cryogenic Associative Processor organization and to study its possible use in a variety of Aerospace applications. Two approaches were considered to this problem: one in which an associative memory would be added to a more or less conventional ...
Richard G. Ewing, Paul M. Davies
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This paper describes the computer system designed under an Air Force sponsored study program to develop a non-cryogenic Associative Processor organization and to study its possible use in a variety of Aerospace applications. Two approaches were considered to this problem: one in which an associative memory would be added to a more or less conventional ...
Richard G. Ewing, Paul M. Davies
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Beyond processor sharing [PDF]
Performance Evaluation Review, 2007 While the (Egalitarian) Processor-Sharing (PS) discipline offers crucial insights in the performance of fair resource allocation mechanisms, it is inherently limited in analyzing and designing differentiated scheduling algorithms such as Weighted Fair Queueing and Weighted Round-Robin.
Samuli Aalto, Urtzi Ayesta, Sem Borst
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Determination of processor allocation in the design of processor arrays
Microprocessors and Microsystems, 1998Abstract This paper deals with the design of processor arrays for algorithms which can be represented as systems of uniform recurrence equations. We present an approach to determine allocation functions as part of this design. The objective of our approach is to generate allocation functions minimizing the necessary chip area for a hardware ...
Dirk Fimmel, Renate Merker
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Proceedings of the December 5-7, 1972, fall joint computer conference, part I on - AFIPS '72 (Fall, part I), 1972
In the interest of improving readability, instruction retry is presented generically. Technical terms unique to the 6000 are avoided.
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In the interest of improving readability, instruction retry is presented generically. Technical terms unique to the 6000 are avoided.
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Implementation of an image signal processor for reconfigurable processors
2014 IEEE International Conference on Consumer Electronics (ICCE), 2014An image signal processor for a CMOS image sensor consists of many complicated functions. In this paper, the full chain of camera ISP functions for smart devices is presented. The every function in the chain is fully converted to fixed point arithmetic and no special function is used for easy porting to reconfigurable processors.
Seung Hyun Choi +3 more
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