Results 271 to 280 of about 207,528 (316)
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The Expression Processor: A Pipelined, Multiple- Processor Architecture
IEEE Transactions on Computers, 1981A nem multiple-processor architecture is described that can exploit the instruction level concurrency in numerical processing tasks. The expression processor contains multiple processing elements (PE's), which can be configured either as an SIMD [8] array or as an expression tree pipeline.
Jerry R. Van Aken, Gregory L. Zick
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Determination of the processor functionality in the design of processor arrays
Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2002In this paper the inclusion of hardware constraints into the design of massively parallel processor arrays is considered. We propose an algorithm which determines an optimal scheduling function as well as the selection of components which have to be implemented in one processor of a processor array.
Dirk Fimmel, Renate Merker
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Processors and Their Collection
2012In a flexible approach to concurrent computation, "processors" ' (computational resources such as threads) are allocated dynamically, just as objects are; but then, just as objects, they can become unused, leading to performance degradation or worse. We generalized the notion of garbage collection (GC), traditionally applied to objects, so that it also
Bertrand Meyer 0001 +2 more
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Celestial Mechanics and Dynamical Astronomy, 2001
In this paper, a semi-analytical solution of the Kustaanheimo-Stiefel equation for the perturbed Kepler problem was developed. The procedure which is used, here, is capable of building the solution in a semi-analytical form serving as an efficient ``quaternionic'' processor.
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In this paper, a semi-analytical solution of the Kustaanheimo-Stiefel equation for the perturbed Kepler problem was developed. The procedure which is used, here, is capable of building the solution in a semi-analytical form serving as an efficient ``quaternionic'' processor.
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Power Efficient Processor Architecture and The Cell Processor
11th International Symposium on High-Performance Computer Architecture, 2005This paper provides a background and rationale for some of the architecture and design decisions in the cell processor, a processor optimized for compute-intensive and broadband rich media applications, jointly developed by Sony Group, Toshiba, and IBM. The paper discusses some of the challenges microprocessor designers face and provides motivation for
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Multicore processors as Array Processors: Research Opportunities
IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), 2006We first argue that the spectrum of processor architectures-from general-purpose processors (GPPs) to application-specific processors (ASPs) to FPGA coprocessors is narrowing (but not converging), due to some dominating physical and economic forces. We then suggest some research opportunities driven by these forces.
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Programmable Quantum Processors
Quantum Information Processing, 2006zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Vladimír R. Buzek +3 more
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IEEE Transactions on Computers, 1970
The Berkeley array processor is a special-purpose computer designed to perform the operations of correlation, convolution, recursive filtering, matrix multiplication, as well as a variant of the Cooley-Tukey algorithm, and others. This note describes the logical organization and performance of this device.
Warren Y. Dere, David J. Sakrison
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The Berkeley array processor is a special-purpose computer designed to perform the operations of correlation, convolution, recursive filtering, matrix multiplication, as well as a variant of the Cooley-Tukey algorithm, and others. This note describes the logical organization and performance of this device.
Warren Y. Dere, David J. Sakrison
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The Coherent Processor: an associative processor architecture and applications
COMPCON Spring '91 Digest of Papers, 2002The Coherent Processor (CP), a massively parallel computer based on content addressable memory, is discussed. The CP offers advantages such as high performance, low cost, low weight, low power consumption, and a simple system interface and programming model. These features make it well-suited for real-time and embedded systems.
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