Results 211 to 220 of about 15,198 (259)

LEAP: A Data Driven Loop Engine on Array Processor

Lecture Notes in Computer Science, 2003
This paper presents a novel architecture for array processor, called LEAP, which is a set of simple processing elements. The targeted programs are innermost loops. By using the technique called if-conversion, the control dependence can be converted to data dependence to prediction variables.
Yong Dou, Xicheng Lu
openaire   +3 more sources

Processor-in-the-loop and hardware-in-the-loop simulation of electric systems based in FPGA

2016 13th International Conference on Power Electronics (CIEP), 2016
Processor-in-the-loop (PIL) is a test technique that allows designers to evaluate a controller, running in a dedicated processor, of a plant which runs in an offline simulation platform. By the other side, Hardware-in-the-Loop (HIL) is an approach to test a plant or controller running in a digital platform which interacts with the real controller or ...
J. Mina, Z. Flores, E. Lopez, A. Perez, J.-H. Calleja   +4 more
openaire   +3 more sources

Evaluation of Attitude Determination Algorithms via Model-in-the-Loop and Processor-in-the-Loop

Journal of Aerospace Engineering, 2023
Seyed Majid Esmaeilzadeh, Mostafa Shahrezaei   +1 more
openaire   +3 more sources

Scheduling sequential loops on parallel processors

SIAM Journal on Computing, 1988
Automatic parallelization of code written in a sequential language such as FORTRAN is of great importance for compilers for parallel computers. First, the problem of automatically parallelizing iterative loops on multiprocessors is discussed, and then a scheduling problem involving precedence constraints that models a technique for the automatic ...
Ashfaq A. Munshi, Barbara Simons
openaire   +1 more source

Processor Aware Anticipatory Prefetching in Loops

10th International Symposium on High Performance Computer Architecture (HPCA'04), 2005
As microprocessor speeds increase, a large fraction of the execution time is often lost to cache miss penalties. This loss can be particularly severe in processors such as the UltraSPARC-IIICu which have in-order execution and block on cache misses. Such processors rely greatly on the compiler to reduce stalls and achieve high performance.
Spiros Kalogeropulos, Mahadevan Rajagopalan, Vikram Rao, Yonghong Song, Partha Tirumalai   +4 more
openaire   +1 more source

Function inlining and loop unrolling for loop acceleration in reconfigurable processors

Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems, 2012
The next generation SoCs for consumer electronics need software solutions for faster time-to-market, lower development cost and higher performance while maintaining lower energy consumption and area. As a result, reconfigurable processors (RPs) have become increasingly important, which enables just enough exibility of accepting software solutions and ...
Narasinga Rao Miniskar, Pankaj Shailendra Gode, Soma Kohli, Donghoon Yoo   +3 more
openaire   +1 more source

Processor preallocation and load balancing of DOALL loops

The Journal of Supercomputing, 1994
Load balance is important because it may affect the speedup attained through the concurrent execution of loop iterations on a parallel processor. We study loop load balance in the context of the well-known Perfect benchmarks. Several static and dynamic characteristics of the Perfect benchmark DOALL loops are observed and interpreted. Thelate arrival of
Gary Elsesser, Viet N. Ngo, Sourav Bhattacharya, Wei-Tek Tsai   +3 more
openaire   +1 more source

Loop Scheduling for Transport Triggered Architecture Processors

2006 International Symposium on System-on-Chip, 2006
Compilation of programs for highly parallel processors requires efficient scheduling of parallel resources. The innermost loops should achieve the highest throughput possible with the available resources. In this paper, a scheduling method for transport triggered architecture (TTA) processors is proposed.
Perttu Salmela, Risto Mäkinen, Pekka Jääskeläinen, Jarmo Takala   +3 more
openaire   +1 more source

Defensive loop tiling for multi-core processor

Proceedings of the 2012 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, 2012
Loop tiling is a compiler transformation that tailors an application's working set to fit in a cache hierarchy. On today's multicore processors, part of the hierarchy, especially the last level cache (LLC) is shared. In this paper, we show that cache sharing requires special types of tiling depending on the co-run programs.
Bin Bao, Xiaoya Xiang
openaire   +1 more source

Processor allocation and loop scheduling on multiprocessor computers

Proceedings of the 6th international conference on Supercomputing - ICS '92, 1992
This paper is concerned with the automatic exploitation of the parallelism detected in a sequential program. The target machine is a shared memory multiprocessor.The main goal is minimizing the completion time of the program. To achieve this, one has first to distribute the code over the processors, then to schedule the parts of the code in order to ...
Nadia Tawbi, Paul Feautrier
openaire   +1 more source