Results 221 to 230 of about 15,198 (259)
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Parallel processor balance through loop spreading
Proceedings of the 1989 ACM/IEEE conference on Supercomputing - Supercomputing '89, 1989When the number of processors P is less than the number of tasks N in a parallel loop, the loop has to be executed in ⌈N/P⌉ rounds and the last round executes only (N mod P) tasks. In many cases, in the last round all but a few processors are idle, which causes a significant drop in performance.
Youfeng Wu, Ted G. Lewis
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LPA: A First Approach to the Loop Processor Architecture
2008Current processors frequently run applications containing loop structures. However, traditional processor designs do not take into account the semantic information of the executed loops, failing to exploit an important opportunity. In this paper, we take our first step toward a loop-conscious processor architecture that has great potential to achieve ...
Alejandro García +4 more
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Time and Parallel Processor Bounds for Fortran-Like Loops
IEEE Transactions on Computers, 1979The main goal of this paper is to show that a large number of processors can be used effectively to speed up simple Fortran-like loops consisting of assignment statements. A practical method is given by which one can check whether or not a statement is dependent upon another. The dependence structure of the whole loop may be of different types.
Utpal Banerjee +3 more
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Processor-In-the-Loop Simulation
2017Empowered by the increasing computational power broadly available in current computer technology, the use of simulation software is an ubiquitous approach both in academia and industry during the development path of a large number of systems.
Rómulo Antão +3 more
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A Digital Open-Loop Adaptive Processor
IEEE Transactions on Aerospace and Electronic Systems, 1978A new technique for adaptive processing applications, which is superior to the conventional Applebaum-Howells adaptive loop, is presented. The new technique is based on open-loop digital processing and does not have the limitations of the conventional closedloop analog processor.
Frank Kretschmer, Bernard Lewis
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Phase locked loops for array processors
ICCSC'02. 1st IEEE International Conference on Circuits and Systems for Communications. Proceedings (IEEE Cat. No.02EX605), 2003In modern computers the processor synchronization problem arises. In array processors the clock skew may be significant. The last may lead to the incorrect working of parallel algorithms. The problem of a clock skew in high-speed systems is so important that modern VLSI chips are often supplied by several phase locked loops, placed on one chip. In this
G.A. Leonov, S.M. Seledzhi
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Design and Construction of Looped Parallel Processors
Optical Computing, 1993Recent advances in device technology have indicated that the role of optics in information processing systems will be in providing non-local interconnections between devices, with logic performed by the electronics.
S. Wakelin, F.A.P. Tooley
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Embedded processors optimization with hardware in the loop
2004 IEEE International Symposium on Industrial Electronics, 2004The design of an embedded microprocessor for a given workload is a tremendous task by itself due to the numerous parameters involved and the ranges of their possible values. If power consumption and area are also to be considered then the problem is even more complicated and requires a suitable framework and methodology for exploring the vast ...
K. Ghali, O. Hammami
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Revolver: Processor architecture for power efficient loop execution
2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), 2014With the rise of mobile and cloud-based computing, modern processor design has become the task of achieving maximum power efficiency at specific performance targets. This trend, coupled with dwindling improvements in single-threaded performance, has led architects to predominately focus on energy efficiency.
Mitchell Hayenga +2 more
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A monolithic phase-locked loop with post detection processor
IEEE Journal of Solid-State Circuits, 1979Describes the design and fabrication of a high-frequency (50-MHz) phase-locked loop with a post detection processor which allows the detection of FSK signals with few external components. The circuit operates with a single 5-V supply and has TTL compatible inputs and outputs.
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