Results 241 to 250 of about 149,979,854 (294)

LEAP: A Data Driven Loop Engine on Array Processor

Lecture Notes in Computer Science, 2003
This paper presents a novel architecture for array processor, called LEAP, which is a set of simple processing elements. The targeted programs are innermost loops. By using the technique called if-conversion, the control dependence can be converted to data dependence to prediction variables.
Xicheng Lu
exaly   +3 more sources

Scheduling sequential loops on parallel processors

SIAM Journal on Computing, 1988
Automatic parallelization of code written in a sequential language such as FORTRAN is of great importance for compilers for parallel computers. First, the problem of automatically parallelizing iterative loops on multiprocessors is discussed, and then a scheduling problem involving precedence constraints that models a technique for the automatic ...
Ashfaq A. Munshi, Barbara Simons
openaire   +2 more sources

Processor Aware Anticipatory Prefetching in Loops

10th International Symposium on High Performance Computer Architecture (HPCA'04), 2005
As microprocessor speeds increase, a large fraction of the execution time is often lost to cache miss penalties. This loss can be particularly severe in processors such as the UltraSPARC-IIICu which have in-order execution and block on cache misses. Such processors rely greatly on the compiler to reduce stalls and achieve high performance.
Spiros Kalogeropulos, Mahadevan Rajagopalan, Vikram Rao, Yonghong Song, Partha Tirumalai   +4 more
openaire   +1 more source

Function inlining and loop unrolling for loop acceleration in reconfigurable processors

Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems, 2012
The next generation SoCs for consumer electronics need software solutions for faster time-to-market, lower development cost and higher performance while maintaining lower energy consumption and area. As a result, reconfigurable processors (RPs) have become increasingly important, which enables just enough exibility of accepting software solutions and ...
Narasinga Rao Miniskar, Pankaj Shailendra Gode, Soma Kohli, Donghoon Yoo   +3 more
openaire   +1 more source

Parallel processor balance through loop spreading

Proceedings of the 1989 ACM/IEEE conference on Supercomputing - Supercomputing '89, 1989
When the number of processors P is less than the number of tasks N in a parallel loop, the loop has to be executed in ⌈N/P⌉ rounds and the last round executes only (N mod P) tasks. In many cases, in the last round all but a few processors are idle, which causes a significant drop in performance.
Youfeng Wu, Ted G. Lewis
openaire   +1 more source

Processor allocation and loop scheduling on multiprocessor computers

Proceedings of the 6th international conference on Supercomputing - ICS '92, 1992
This paper is concerned with the automatic exploitation of the parallelism detected in a sequential program. The target machine is a shared memory multiprocessor.The main goal is minimizing the completion time of the program. To achieve this, one has first to distribute the code over the processors, then to schedule the parts of the code in order to ...
Nadia Tawbi, Paul Feautrier
openaire   +1 more source

Loop Scheduling for Transport Triggered Architecture Processors

2006 International Symposium on System-on-Chip, 2006
Compilation of programs for highly parallel processors requires efficient scheduling of parallel resources. The innermost loops should achieve the highest throughput possible with the available resources. In this paper, a scheduling method for transport triggered architecture (TTA) processors is proposed.
Perttu Salmela, Risto Mäkinen, Pekka Jääskeläinen, Jarmo Takala   +3 more
openaire   +1 more source

Processor-In-the-Loop Simulation

2017
Empowered by the increasing computational power broadly available in current computer technology, the use of simulation software is an ubiquitous approach both in academia and industry during the development path of a large number of systems.
Rómulo Antão, Alexandre Mota, Rui Escadas Martins, José Tenreiro Machado   +3 more
openaire   +1 more source

Defensive loop tiling for multi-core processor

Proceedings of the 2012 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, 2012
Loop tiling is a compiler transformation that tailors an application's working set to fit in a cache hierarchy. On today's multicore processors, part of the hierarchy, especially the last level cache (LLC) is shared. In this paper, we show that cache sharing requires special types of tiling depending on the co-run programs.
Bin Bao, Xiaoya Xiang
openaire   +1 more source

Phase locked loops for array processors

ICCSC'02. 1st IEEE International Conference on Circuits and Systems for Communications. Proceedings (IEEE Cat. No.02EX605), 2003
In modern computers the processor synchronization problem arises. In array processors the clock skew may be significant. The last may lead to the incorrect working of parallel algorithms. The problem of a clock skew in high-speed systems is so important that modern VLSI chips are often supplied by several phase locked loops, placed on one chip. In this
G.A. Leonov, S.M. Seledzhi
openaire   +1 more source