Results 231 to 240 of about 15,198 (259)

A scalable loop optimization approach for scalable DSP processors

2000 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.00CH37100), 2002
This paper proposes the possibility of reuse of the existing optimized DSP code on a scalable high-performance VLIW DSP processor. Since loops are the critical paths in most DSP applications, we focus on issues related to loop optimization. In our approach, we first perform a loop alignment transformation on the source level; we then reuse the existing
Jian Wang 0046, Bogong Su, Erh-Wen Hu
openaire   +1 more source

GENERATING CLOSE TO OPTIMUM LOOP SCHEDULES ON PARALLEL PROCESSORS

Parallel Processing Letters, 1994
This paper addresses the NP-hard problem of scheduling a cyclic set of interdependent operations, representing a program loop, when a finite number of identical pipelined or unpipelined processors are available. We give a simple and efficient algorithm which provably produces close to optimum results.
Franco Gasperoni, Uwe Schwiegelshohn
openaire   +1 more source

Processor self-scheduling for parallel loops in preemptive environments

Future Generation Computer Systems, 1990
Abstract Processor self-scheduling schemes for parallel loops can be used in a non-preemptive environment to reduce the scheduling overhead significantly. In a preemptive environment system like Cray X-MP/4, the schemes can cause serious problems. In this paper, we describe the problems of processor self-scheduling schemes in a preemptive environment.
Xuejun Yang, Haibo Chen 0004, Yungui Ci, Fujie Chen, Lijie Chen 0005   +4 more
openaire   +1 more source

Symbolic Mapping of Loop Programs onto Processor Arrays

Journal of Signal Processing Systems, 2014
In this paper, we present a solution to the problem of joint tiling and scheduling a given loop nest with uniform data dependencies symbolically. This challenge arises when the size and number of available processors for parallel loop execution is not known at compile time.
Jürgen Teich, Alexandru Tanase, Frank Hannig   +2 more
openaire   +1 more source

Mapping of Affine Loop Nests onto Independent Processors

Cybernetics and Systems Analysis, 2003
zbMATH Open Web Interface contents unavailable due to conflicting licenses.
openaire   +2 more sources

Loop recreation for thread‐level speculation on multicore processors

Software: Practice and Experience, 2009
AbstractInter‐iteration dependences in loops can hinder loop‐level parallelism. For some loops, existing thread‐level speculation techniques fail to expose their inherent loop‐level parallelism, because some inter‐iteration dependences are too costly to synchronize, predict, pre‐compute and isolate.
Lin Gao 0002, Jingling Xue, Tin-Fook Ngai   +2 more
openaire   +1 more source

Memory performance model for loops and kernels on power3 processors

18th International Parallel and Distributed Processing Symposium, 2004. Proceedings., 2004
Summary form only given. A performance model for loops and kernels limited by memory access is developed that is applicable to Power3 processors. The output of the model is the time delay arising from cache and TLB misses. The input variables are the miss rates of each cache and the TLB, while the model parameters are the miss penalties of each cache ...
openaire   +1 more source

STABILITY AND BIFURCATIONS OF PHASE-LOCKED LOOPS FOR DIGITAL SIGNAL PROCESSORS

International Journal of Bifurcation and Chaos, 2005
For continuous and discrete floating phase-locked loops, conditions of local and global stability are obtained. For discrete systems, period-doubling bifurcations are described. The results obtained are applied to the solution of the problem of eliminating the clock skew in digital signal processors.
Gennady A. Leonov, Svetlana M. Seledzhi
openaire   +1 more source

Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms

The Journal of Supercomputing, 2003
zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Marcus Bednara, Jürgen Teich
openaire   +2 more sources

A Monolithic PhaseLocked Loop with Detection Processor

2009
This paper details the design and fabrication of a highfrequency (50-MHz) phase-locked loop with a post detection processor which allows the detection of FSK signals with few external components. The circuit operates with a single 5-V supply and has TIL compatible inputs and outputs.
openaire   +1 more source