Results 251 to 260 of about 149,979,854 (294)

A Digital Open-Loop Adaptive Processor

IEEE Transactions on Aerospace and Electronic Systems, 1978
A new technique for adaptive processing applications, which is superior to the conventional Applebaum-Howells adaptive loop, is presented. The new technique is based on open-loop digital processing and does not have the limitations of the conventional closedloop analog processor.
Frank Kretschmer, Bernard Lewis
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Design and Construction of Looped Parallel Processors

Optical Computing, 1993
Recent advances in device technology have indicated that the role of optics in information processing systems will be in providing non-local interconnections between devices, with logic performed by the electronics.
S. Wakelin, F.A.P. Tooley
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A monolithic phase-locked loop with post detection processor

IEEE Journal of Solid-State Circuits, 1979
Describes the design and fabrication of a high-frequency (50-MHz) phase-locked loop with a post detection processor which allows the detection of FSK signals with few external components. The circuit operates with a single 5-V supply and has TTL compatible inputs and outputs.
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Embedded processors optimization with hardware in the loop

2004 IEEE International Symposium on Industrial Electronics, 2004
The design of an embedded microprocessor for a given workload is a tremendous task by itself due to the numerous parameters involved and the ranges of their possible values. If power consumption and area are also to be considered then the problem is even more complicated and requires a suitable framework and methodology for exploring the vast ...
K. Ghali, O. Hammami
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Revolver: Processor architecture for power efficient loop execution

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), 2014
With the rise of mobile and cloud-based computing, modern processor design has become the task of achieving maximum power efficiency at specific performance targets. This trend, coupled with dwindling improvements in single-threaded performance, has led architects to predominately focus on energy efficiency.
Mitchell Hayenga, Vignyan Reddy Kothinti Naresh, Mikko H. Lipasti   +2 more
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GENERATING CLOSE TO OPTIMUM LOOP SCHEDULES ON PARALLEL PROCESSORS

Parallel Processing Letters, 1994
This paper addresses the NP-hard problem of scheduling a cyclic set of interdependent operations, representing a program loop, when a finite number of identical pipelined or unpipelined processors are available. We give a simple and efficient algorithm which provably produces close to optimum results.
Franco Gasperoni, Uwe Schwiegelshohn
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Processor self-scheduling for parallel loops in preemptive environments

Future Generation Computer Systems, 1990
Abstract Processor self-scheduling schemes for parallel loops can be used in a non-preemptive environment to reduce the scheduling overhead significantly. In a preemptive environment system like Cray X-MP/4, the schemes can cause serious problems. In this paper, we describe the problems of processor self-scheduling schemes in a preemptive environment.
Xuejun Yang, Haibo Chen 0004, Yungui Ci, Fujie Chen, Lijie Chen 0005   +4 more
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Loop recreation for thread‐level speculation on multicore processors

Software: Practice and Experience, 2009
AbstractInter‐iteration dependences in loops can hinder loop‐level parallelism. For some loops, existing thread‐level speculation techniques fail to expose their inherent loop‐level parallelism, because some inter‐iteration dependences are too costly to synchronize, predict, pre‐compute and isolate.
Lin Gao 0002, Jingling Xue, Tin-Fook Ngai   +2 more
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Symbolic Mapping of Loop Programs onto Processor Arrays

Journal of Signal Processing Systems, 2014
In this paper, we present a solution to the problem of joint tiling and scheduling a given loop nest with uniform data dependencies symbolically. This challenge arises when the size and number of available processors for parallel loop execution is not known at compile time.
Jürgen Teich, Alexandru Tanase, Frank Hannig   +2 more
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Memory performance model for loops and kernels on power3 processors

18th International Parallel and Distributed Processing Symposium, 2004. Proceedings., 2004
Summary form only given. A performance model for loops and kernels limited by memory access is developed that is applicable to Power3 processors. The output of the model is the time delay arising from cache and TLB misses. The input variables are the miss rates of each cache and the TLB, while the model parameters are the miss penalties of each cache ...
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