Results 261 to 270 of about 878,159 (309)

Transistor sizing for radiation hardening

2004 IEEE International Reliability Physics Symposium. Proceedings, 2004
This paper presents an efficient and accurate numerical analysis technique to simulate single event upsets (SEUs) in logic circuits. Experimental results that show the method is accurate to within 10% of the results obtained using SPICE are provided.
null Quming Zhou, K. Mohanram
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Radiation Hardened by Design

2015
The major work introduced in this book is to develop a megagray-radiation-tolerant ps-resolution time-to-digital converter (TDC) for a light detection and ranging (LIDAR) application. In this chapter, major radiation effects in complementary metal–oxide–semiconductor (CMOS) integrated circuits (ICs) are introduced. The total ionizing dose (TID) effects
Ying Cao, Paul Leroux, Michiel Steyaert
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On the saturation of radiation hardening

Physics Letters A, 1969
Abstract A model of saturation of radiation hardening is given. This model suggests that saturation of the thermal hardening component should occur at different fluence levels than would the athermal component.
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Radiation-hardened microelectronics for accelerators

IEEE Transactions on Nuclear Science, 1988
Ionization and displacement phenomena in semiconducting materials are reviewed. How these basic effects lead to changes in the electrical characteristics of transistors and diodes and the functionality of integrated circuits are discussed. The fundamental radiation limits for various semiconductor technologies are summarized.
J.E. Gover, T.A. Fischer
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Radiation Hardened by Design Sense Amplifier

2019
This paper presents a fully symmetrical radiation hardened sense amplifier is designed in and 32 nm FinFET Double gate PTM technology to tolerate single node upset and multiple-node upset.circuit. A 9 pC charge is used at critical node of the sense amplifier to analyse Single Event Transient.
Avinash Verma, Gaurav Kaushal
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Radiation Hardened CMOS/SOS

IEEE Transactions on Nuclear Science, 1975
This paper reports the results of experiments designed to optimize the total dose ionizing radiation hardness of CMOS/SOS devices. Type 4007 inverter circuits were fabricated with variations in the process, including wet versus dry gate oxidation. Tolerable values (e. g.
K. G. Aubuchon, E. Harari
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Radiation-hardening of semiconductor parts

2002
Abstract ‘Radiation-hardening’ derives from military terminology (see Section 4.1). The term has acquired a wide variety of meanings, depending on the user group and radiation environment concerned. That environment may present a variety of levels of total ionizing dose, transient dose rate, neutrons, or single-event upsets.
Andrew Holmes-Siedle, Len Adams
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Radiation hardening in Zircaloy-2

Radiation Effects, 1973
Abstract Annealed Zircaloy-2 was exposed to fast neutron fluences in the range 0.46 to 6.71 × 1019 nvt, E > 1 MeV, at temperatures of up to 450°C. The level of radiation hardening, as measured by the change in yield stress after irradiation, increased with irradiation temperature at least up to 380°C.
K. U. Snowden, K. Veevers
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Radiation Hardening by Process

2017
This chapter describes the approaches for optimization of semiconductor device fabrication processes and structures to mitigate radiation effects in advanced silicon-based technologies, primarily complementary metal oxide semiconductor (CMOS). It discusses effects and mitigation approaches related to insulators, active device regions, and process ...
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The avenue of FDSOI radiation hardening

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014
Advanced FDSOI technology has inherent resistance to transient ionizing radiation effects and better Single Event Effect (SEE) tolerance. In the meantime, total dose hardening is now the biggest challenging for the cutting-edge FDSOI technology. Three TID hardening techniques are discussed in this paper. The effects of buried oxide modification, device
Kai Zhao, Zhongli Liu, Fang Yu
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