Results 11 to 20 of about 9,109,748 (351)
Trusted Hart for Mobile RISC-V Security [PDF]
2022 IEEE International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom), 2022 This is an extended version of a paper that has been published in Proceedings of TrustCom ...
V. Ushakov +6 more
core +4 more sources
Analysis on the Possibility of RISC-V Adoption [PDF]
UC Merced Undergraduate Research Journal, 2020 Author(s): Scott, Ian | Abstract: As the interface between hardware and software, Instruction Set Architectures (ISAs) play a key role in the operation of computers. While both hardware and software have continued to evolve rapidly over time, ISAs have undergone minimal change.
Scott, Ian
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Implementation of RISC-V Processor [PDF]
ITM Web of ConferencesThis work focuses on implementation/designing the RISC-V Processor with optimized pipeline throughput, cache hit rate, and dynamic instruction scheduling to enhance the processing speed and energy efficiency. RISC-V extension used to support the tasks in
Saiprathyusha P., Chandrasekhar C.
doaj +2 more sources
Hypervisor Extension for a RISC-V Processor
2023 RISC-V Summit Europe, 2023 This work is partially supported by the DRAC (IU16-011591), the HORIZON Vitamin-V (101093062) and the Computación de Altas Prestaciones VIII (PID2019-107255GB) projects.
Gauchola Vilardell, Jaume +10 more
openaire +4 more sources
Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU [PDF]
SC Workshops, 2023 The Sophon SG2042 is the world’s first commodity 64-core RISC-V CPU for high performance workloads and an important question is whether the SG2042 has the potential to encourage the HPC community to embrace RISC-V.
Nick Brown +3 more
semanticscholar +3 more sources
Optimized Hardware-Software Co-Design for Kyber and Dilithium on RISC-V SoC FPGA
Transactions on Cryptographic Hardware and Embedded SystemsKyber and Dilithium are both lattice-based post-quantum cryptography (PQC) algorithms that have been selected for standardization by the American National Institute of Standards and Technology (NIST). NIST recommends them as two primary algorithms to be
Tengfei Wang +4 more
doaj +2 more sources
Satellite Onboard Data Reduction Using a Risc-V Core Inside an RTG4-Based Data Processing Pipeline [PDF]
Architecture of Computing Systems – ARCS 202033rd International Conference, 2020 Skvarc Bozic G, Ott S, Plattner M.
europepmc +3 more sources
A RISC-V SystemC-TLM simulator [PDF]
, 2020 This work presents a SystemC-TLM based simulator for a RISC-V microcontroller. This simulator is focused on simplicity and easy expandable of a RISC-V. It is built around a full RISC-V instruction set simulator that supports full RISC-V ISA and extensions M, A, C, Zicsr and Zifencei.
Màrius
+6 more sources
Functional Verification of a RISC-V Vector Accelerator [PDF]
IEEE Design & Test, 2022 We present the functional verification efforts for an academic RISC-V based vector accelerator, successfully taped-out in the context of the European Processor Initiative. For our novel RISC-V based decoupled vector accelerator, we built a verification infrastructure consisting of a UVM environment, performing step by step co-simulation of all vector ...
Víctor Jiménez +11 more
openalex +5 more sources
Return-Oriented Programming in RISC-V
, 2020 RISC-V is an open-source hardware ISA based on the RISC design principles, and has been the subject of some novel ROP mitigation technique proposals due to its open-source nature. However, very little work has actually evaluated whether such an attack is feasible assuming a typical RISC-V implementation.
Garrett Gu, Hovav Shacham
openalex +4 more sources