Results 11 to 20 of about 13,809 (235)
Optimization Strategy of FFmpeg Multimedia Algorithm Library Based on RISC-V [PDF]
Jisuanji gongcheng, 2023 The widespread application of RISC-V processors has made the high-performance implementation of FFmpeg multimedia algorithm library on the RISC-V platform increasingly important.This study proposes a series of RISC-V architecture-based optimization ...
ZHANG Zhen, LIANG Jun, JIA Haipeng, ZHANG Yunquan, LI Qing
doaj +1 more source
Proceedings of the 52nd ACM Technical Symposium on Computer Science Education, 2021 We describe our experience teaching an undergraduate capstone (and elective graduate course) in computer architecture with a semester-long project in which teams of five students design and implement an out-of-order (OoO) pipelined processor core using the open-source RISC-V instruction set.
Stephen A. Zekany +3 more
openaire +1 more source
A Survey of the RISC-V Architecture Software Support
IEEE Access, 2022 RISC-V is a novel open instruction set architecture that supports multiple platforms while maintaining simplicity and reliability. Despite its novelty, the software support for RISC-V has been increasing in the last years, given that popular toolchains ...
Benjamin W. Mezger +4 more
doaj +1 more source
IEEE Access, 2021 A trusted execution environment (TEE) is a new hardware security feature that is isolated from a normal OS (i.e., rich execution environment (REE)). The TEE enables us to run a critical process, but the behavior is invisible from the normal OS, which ...
Kuniyasu Suzaki +3 more
doaj +1 more source
Developing a Multicore Platform Utilizing Open RISC-V Cores
IEEE Access, 2021 RISC-V has been experiencing explosive growth since its first appearance in 2011. Dozens of free and open cores developed based on this instruction set architecture have been released, and RISC-V based devices optimized for specific applications such as ...
Hyeonguk Jang +6 more
doaj +1 more source
Holistic RISC-V Virtualization
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023 This work describes our efforts to provide a holistic hardware RISC-V virtualization SoC based on the CVA6 core. At the core level, we implemented hardware support for virtualization through the ratified Hypervisor instruction set architecture (ISA) extension version 1.0.
Bruno Sá +4 more
openaire +2 more sources
LLVM RISC-V RV32X Graphics Extension Support and Characteristics Analysis of Graphics Programs
IEEE Access, 2023 In recent years, virtual reality technology has become the dominant means of human-computer interaction, with computer graphics rendering technology being a crucial component in realizing virtual reality experiences.
Peng Wang, Zhi-Bin Yu
doaj +1 more source
Journal of Low Power Electronics and Applications, 2022 With the growing popularity of RISC-V and various open-source released RISC-V processors, it is now possible for computer engineers students to explore this simple and relevant architecture, and also, these students can explore and design a ...
Peter Jamieson +7 more
doaj +1 more source
Backporting RISC-V Vector Assembly
, 2023 Leveraging vectorisation, the ability for a CPU to apply operations to multiple elements of data concurrently, is critical for high performance workloads. However, at the time of writing, commercially available physical RISC-V hardware that provides the RISC-V vector extension (RVV) only supports version 0.7.1, which is incompatible with the latest ...
Joseph K. L. Lee +2 more
openaire +2 more sources
IEEE Access, 2020 This study describes the design and implementation of a 256-bit very long instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA).
Nguyen My Qui, Chang Hong Lin, Poki Chen
doaj +1 more source