Results 31 to 40 of about 9,109,748 (351)
IEEE Access, 2020 This study describes the design and implementation of a 256-bit very long instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA).
Nguyen My Qui, Chang Hong Lin, Poki Chen
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Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype
Journal of Low Power Electronics and Applications, 2022 RISC-V is a modern Instruction Set Architecture (ISA) that, by its open nature in combination with a clean and modular design, has enormous potential to become a game changer in the Internet of Things (IoT) era. Recently, SystemC-based Virtual Prototypes
Pascal Pieper +2 more
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Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2–8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing [PDF]
IEEE Journal of Solid-State Circuits, 2023 Emerging artificial intelligence-enabled Internet-of-Things (AI-IoT) system-on-chip (SoC) for augmented reality, personalized healthcare, and nanorobotics need to run many diverse tasks within a power envelope of a few tens of mW over a wide range of ...
Francesco Conti +9 more
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RISC-V for genome data analysis: opportunities and challenges [PDF]
, 2023 The RISC-V ISA has gained significant momentum in High-Performance Computing (HPC) research and market due to its open-source nature, fostering collaborative research and innovation.
Alastruey Benedé, Jesús +6 more
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DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training [PDF]
IEEE Open Journal of the Solid-State Circuits Society, 2023 On-chip deep neural network (DNN) inference and training at the Extreme-Edge (TinyML) impose strict latency, throughput, accuracy, and flexibility requirements.
Angelo Garofalo +7 more
semanticscholar +1 more source
Proceedings of the Institute for System Programming of the RAS, 2020 An Instruction Set Architecture (ISA) is the core around which the rest of the CPU is built. Errors or inflexibility in decisions once embedded in a system of instructions remain with this generation of processors forever. Therefore, one of the key reasons why the performance growth of modern CPUs has slowed down is that the source code of the ...
Vladimir Alexandrovitch Frolov +2 more
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The design of scalar AES Instruction Set Extensions for RISC-V
Transactions on Cryptographic Hardware and Embedded Systems, 2020 Secure, efficient execution of AES is an essential requirement on most computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a (relatively) new ISA that lacks such a standardized ISE.
Ben Marshall +4 more
doaj +3 more sources
An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for End-to-End Security in IoT Applications [PDF]
, 1957 This paper presents a reconfigurable cryptographic engine that implements the DTLS protocol to enable end-to-end security for IoT. This implementation of the DTLS engine demonstrates 10x reduction in code size and 438x improvement in energy-efficiency ...
Banerjee, Utsav +4 more
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Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In [PDF]
IEEE Transactions on Circuits and Systems - II - Express Briefs, 2023 Power and cost constraints in the Internet-of-Things (IoT) extreme-edge and TinyML domains, coupled with increasing performance requirements, motivate a trend toward heterogeneous architectures.
A. Ottaviano +3 more
semanticscholar +1 more source
RISER: Raising RISC-V to the cloud
HiPEACInfo magazine, 2023 First public announcement of the RISER ('RISC-V for Cloud Services') project, in the HiPEACInfo magazine (issue Nr. 68, January 2023).
Marazakis, Manolis, Louloudakis, Stelios
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