Results 161 to 170 of about 17,773 (197)

A Low-Power Complementary Metal-Oxide-Semiconductor Receiver with Quadrature Bandpass Continuous-Time Delta-Sigma Analog-to-Digital Converter for IoT Applications. [PDF]

Sensors (Basel)
Kim NS.
europepmc   +1 more source

A Multimodal CMOS Readout IC for SWIR Image Sensors with Dual-Mode BDI/DI Pixels and Column-Parallel Two-Step Single-Slope ADC. [PDF]

Micromachines (Basel)
Zhang Y, Chen Z, Yang Y, Chen H, Gao J, Zhang Z, Chen C.   +6 more
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A 326,000 fps 640 × 480 Resolution Continuous-Mode Ultra-High-Speed Global Shutter CMOS BSI Imager. [PDF]

Sensors (Basel)
Bacq JL, Thite M, Vandebriel R, Mahato SB, Coppejans P, Borremans J, Wu L, Rączkowski K, Cevik I, Motsnyi V, Haspeslagh L, Suess A, Flon B, Jantzen D, Jantzen P, Cavaco C, Spagnolo A.   +16 more
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Non-Linear Modeling and Precision Analysis Approach for Implantable Multi-Channel Neural Recording Systems. [PDF]

Micromachines (Basel)
He J, Xu J, Wang Y.
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Pretargeted Trop-2 ImmunoPET for Rapid, Selective Detection of Pancreatic Tumors. [PDF]

Clin Cancer Res
Pratt EC, Mandleywala K, Bauer D, Bolaender A, Chao G, Castanares MA, Collins EC, Lewis JS.   +7 more
europepmc   +1 more source

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Metastablility in SAR ADCs

IEEE Transactions on Circuits and Systems II: Express Briefs, 2017
The fundamental limitation of Nyquist analog-to-digital converter (ADC) architectures toward high speed is metastability. It refers to the inability of a latched comparator to produce a valid decision in a certain available time. This issue is usually severe in high-speed successive approximation register (SAR) ADCs due to their serial conversion ...
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Boris Murmann, U. Seng-Pan, R.P. Martins   +5 more
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Redundancy in SAR ADCs

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI, 2011
In this paper, we discuss and analyze the effectiveness of redundancy (also known as digital error correction) and its relationship with DAC settling time, comparator delay, digital logic delay and sampling rate in successive-approximation-register (SAR) ADCs.
Albert H. Chang, Hae-Seung Lee, Duane S. Boning   +2 more
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Unified ADC nonlinearity error model for SAR ADC

Measurement, 2008
Abstract The paper introduces a new ADC static nonlinearity model focusing on SAR ADC which is labelled the unified ADC nonlinearity error model. The model can also cover any other ADC architectures that have stochastic and/or periodic extremes in their integral nonlinearity function superposed on a “slowly changing” background. In the proposed model
Linus Michaeli, Peter Michalko, Ján Šaliga   +2 more
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Predictive Noise Shaping SAR ADC

2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019
In this paper, a novel predictive first-order noise shaping SAR ADC is proposed. Noise-shaping (NS) SAR ADCs have recently gained much attention due to their low power requirements and wide dynamic range. However, for any oversampled ADC, there is a range that each sample will be within guaranteed by input bandwidth.
Jyotindra R. Shakya, Ajmal K. Vadakkan, Gabor C. Temes   +2 more
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