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Analog Integrated Circuits and Signal Processing, 2011
A semi-synchronous clocking scheme is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs). The conversion time is dynamically allocated to the comparator decision and to the DAC settling in every bit cycle. This significantly improves the conversion speed.
Tao Tong +2 more
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A semi-synchronous clocking scheme is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs). The conversion time is dynamically allocated to the comparator decision and to the DAC settling in every bit cycle. This significantly improves the conversion speed.
Tao Tong +2 more
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SAR ADC algorithm with redundancy
APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008This paper describes a redundant algorithm for a highly reliable Successive Approximation Register (SAR) ADC where mistakes of comparator decision can be digitally-corrected. We generalize a conventional non-binary search algorithm which requires more conversion steps in the SAR ADC than the binary search algorithm, and clarify which decision errors ...
Tomohiko Ogawa +5 more
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2019
The noise-shaping successive approximation register (NS-SAR) ADC is an emerging hybrid architecture that achieves high resolution and power efficiency simultaneously by combining the merits of the SAR ADC and the Δ Σ ADC. They have the merits of simple, highly digital, and low-voltage tolerant, making them attractive candidates for emerging sensing and
Shaolan Li +3 more
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The noise-shaping successive approximation register (NS-SAR) ADC is an emerging hybrid architecture that achieves high resolution and power efficiency simultaneously by combining the merits of the SAR ADC and the Δ Σ ADC. They have the merits of simple, highly digital, and low-voltage tolerant, making them attractive candidates for emerging sensing and
Shaolan Li +3 more
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Passive reference-sharing SAR ADC
Microelectronics Journal, 2015Charge-redistribution successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used for their simple architecture, inherent low-power consumption and small footprint. Several techniques aiming to reduce the power consumption, to increase the speed, and to reduce the capacitance spread have been developed, such as splitting
Enrique Alvarez-Fontecilla +1 more
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Modified BER Test for SAR ADCs
2020 IEEE International Test Conference in Asia (ITC-Asia), 2020This paper presents a new post-processing method to estimate the real bit error rate (BER) of successive approximation register (SAR) analog-to-digital converters (ADCs) based on the conventional test scheme. Conventional testing method acquires BER based on difference between two measured output codes, rather than between a measured output code and ...
Chia-Chuan Li, Soon-Jyh Chang
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Selectable starting bit SAR ADC
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015Prior work used least-significant bit first quantization (LSBFQ) to conserve switching energy and comparator bitcycles, but is limited to low activity signals. Furthermore, LSBFQ results in a large bitcycle range in the quantizer. A novel selectable starting bit quantizer (SSBQ) is proposed which starts quantization with neither the MSB nor the LSB ...
Jerry Leung, Allen Waters, Un-Ku Moon
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ADC trends and impact on SAR ADC architecture and analysis
2015 IEEE Custom Integrated Circuits Conference (CICC), 2015The performance of ADCs continues to improve with process scaling. For low to moderate resolutions, SAR ADCs deliver the best energy efficiency. Interleaved SAR converters have become popular for very high sampling speeds. The SAR assisted scheme has dramatically improved the energy efficiency of higher resolution pipeline ADCs.
Jeffrey Fredenburg, Michael P. Flynn
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2015
Chapter 2 discussed the basics of the SAR ADCs and their components such as the CDAC or the comparator in detail. Based on these fundamentals, Chap. 3 will present current research topics in the field of SAR ADCs. Generally, the core circuitry of the new SAR ADC should operate from a significantly lower supply voltage compared to the input voltage ...
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Chapter 2 discussed the basics of the SAR ADCs and their components such as the CDAC or the comparator in detail. Based on these fundamentals, Chap. 3 will present current research topics in the field of SAR ADCs. Generally, the core circuitry of the new SAR ADC should operate from a significantly lower supply voltage compared to the input voltage ...
openaire +1 more source