Results 21 to 30 of about 17,773 (197)

A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18µm CMOS Technology [PDF]

Journal of Electrical and Computer Engineering Innovations, 2017
A new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on Capacitor Merged Technique is presented in this paper.
S. Mahdavi
doaj   +1 more source

Implementation of a digital trim scheme for SAR ADCs [PDF]

Advances in Radio Science, 2013
Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975).
J. Bialek, A. Wickmann, F. Ohnhaeuser, G. Fischer, R. Weigel, T. Ussmueller   +5 more
doaj   +1 more source

Sampling and Comparator Speed-Enhancement Techniques for Near-Threshold SAR ADCs

IEEE Open Journal of Circuits and Systems, 2021
This paper presents the sampling and comparator speed-enhancement techniques for SAR ADCs under near-threshold supply voltages. The proposed level-shifted boosting circuit generates sharp falling edges for the sampling clock, which is found a key factor ...
Bojun Hu, Sanfeng Zhang, Xiangxin Pan, Xiangyu Zhao, Zhaoming Ding, Xiong Zhou, Shiheng Yang, Qiang Li   +7 more
doaj   +1 more source

An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC

IEEE Access, 2021
A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed.
Hsuan-Lun Kuo, Chih-Wen Lu, Poki Chen
doaj   +1 more source

Theoretical total harmonic distortion evaluation based on digital to analogue converter mismatch to improve the linearity of successive approximation register analogue to digital converter

IET Circuits, Devices and Systems, 2022
Mismatch in the binary‐weighted capacitive digital‐to‐analog converter (DAC) greatly affects the linearity of the successive‐approximation‐register (SAR) ADC by deteriorating the total harmonic distortion (THD).
Li Dong, Yan Song, Bing Zhang, Zhechong Lan, Youze Xin, Liheng Liu, Ken Li, Xiaofei Wang, Li Geng   +8 more
doaj   +1 more source

A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications [PDF]

, 2016
This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180nm HV CMOS technology, features low switching energy consumption and employs a time-domain ...
Carrasco Robles, Manuel, Delgado Restituto, Manuel, Fiorelli, Rafaella, Ginés Arteaga, Antonio José, Rodríguez Vázquez, Ángel Benito   +4 more
core   +1 more source

A passive second‐order noise‐shaping SAR ADC architecture with increased freedom in NTF synthesis and relaxed clock‐jitter issue

Electronics Letters, 2022
Noise‐shaping (NS) successive approximation register (SAR) analogue‐to‐digital converters (ADCs) are an attractive architecture for power and area efficiency in moderate resolution and bandwidth applications.
Weihao Wang, Xiao Wang, Bo Zhao, Kong‐pang Pun   +3 more
doaj   +1 more source

Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC [PDF]

, 2017
This paper presents mismatch calibration technique to improve the SFDR in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application.
Cen, Yuanjun, Fan, Hua, Heidari, Hadi, Hu, Daqian, Li, Dagang, Maloberti, Franco   +5 more
core   +1 more source

A ZOOM ADC for Protable Gyroscope

Journal of Harbin University of Science and Technology, 2020
This design is a high precision ZOOM analogtodigital converter (ADC) presented for using in microelectromechanical systems (MEMS) gyroscope sensors The structure consists of a successive approximation (SAR) ADC and a Sigma Delta modulator The coarse ...
MEI Jinshuo, CUI Tianbao
doaj   +1 more source

Noise shaping Asynchronous SAR ADC based time to digital converter [PDF]

, 2018
Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits.
Katragadda, Sowmya
core   +1 more source