Results 21 to 30 of about 582,151 (290)
A 14.5-Bit ENOB, 10MS/s SAR-ADC With 2nd Order Hybrid Passive-Active Resonator Noise Shaping
IEEE Access, 2022 A new 2nd order noise shaping (NS) based successive approximation register (SAR) ADC is presented in this paper. In comparison to earlier research, this paper considers hybrid passive-active integrators to compensate for the phase error of the passive ...
Ximing Fu, Kamal El-Sankary
doaj +1 more source
Electronics Letters, 2022 The authors present a low‐power area‐efficient subarray beamforming receiver (RX) structure for a miniaturized 3‐D ultrasound imaging system. Given that the delay‐and‐sum (DAS) and digitization functions consume most of the area and power in the receiver,
Seungah Lee, Soohyun Yun, Joonsung Bae
doaj +1 more source
IEEE Journal of Solid-State Circuits, 2023 Efficient time-interleaved (TI) analog-to-digital converters (ADCs) that operate at high sample rates with wide input bandwidths are necessary to support increasing wireline transceiver data rates. This article presents a 7-bit 38-GS/s 32-way TI ADC that
Yuanming Zhu +8 more
semanticscholar +1 more source
IEEE Journal of Solid-State Circuits, 2023 This article presents a first-order continuous-time (CT) noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC). Different from other NS-SAR ADCs in literature, which are discrete-time (DT), this ADC utilizes a CT Gm-C
Hanyue Li +3 more
semanticscholar +1 more source
A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18µm CMOS Technology [PDF]
Journal of Electrical and Computer Engineering Innovations, 2017 A new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on Capacitor Merged Technique is presented in this paper.
S. Mahdavi
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Implementation of a digital trim scheme for SAR ADCs [PDF]
Advances in Radio Science, 2013 Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975).
J. Bialek +5 more
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Sampling and Comparator Speed-Enhancement Techniques for Near-Threshold SAR ADCs
IEEE Open Journal of Circuits and Systems, 2021 This paper presents the sampling and comparator speed-enhancement techniques for SAR ADCs under near-threshold supply voltages. The proposed level-shifted boosting circuit generates sharp falling edges for the sampling clock, which is found a key factor ...
Bojun Hu +7 more
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IEEE Access, 2021 A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed.
Hsuan-Lun Kuo, Chih-Wen Lu, Poki Chen
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IET Circuits, Devices and Systems, 2022 Mismatch in the binary‐weighted capacitive digital‐to‐analog converter (DAC) greatly affects the linearity of the successive‐approximation‐register (SAR) ADC by deteriorating the total harmonic distortion (THD).
Li Dong +8 more
doaj +1 more source
A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications [PDF]
, 2016 This paper presents a 10-bit fully-differential rail-to-rail successive approximation (SAR) ADC designed for biomedical applications. The ADC, fabricated in a 180nm HV CMOS technology, features low switching energy consumption and employs a time-domain ...
Carrasco Robles, Manuel +4 more
core +1 more source