Results 241 to 250 of about 7,396,207 (304)

Systematic Analysis of the <i>Populus</i> ADF Gene Family and the Expression Patterns Under Osmotic Stress. [PDF]

Life (Basel)
Yang Y, An H, Li HG, Sun Y, Feng B, Li P.   +5 more
europepmc   +1 more source

Heavy Ions Induced Single-Event Transient in SiGe-on-SOI HBT by TCAD Simulation. [PDF]

Micromachines (Basel)
Long Y, Aierken A, Liu X, Liu M, Gao C, Wang G, Wang D, Majumdar S, Xuan Y, Liu M, Bi J.   +10 more
europepmc   +1 more source

Scaling Gaussian Processes for Deterministic Model Predictive Control with Online Updates: A Framework for Model Selection and Re-identification in Process Control. [PDF]

Ind Eng Chem Res
Fouts MW, Mebane DS, Lima FV.
europepmc   +1 more source

A hybrid statistical-machine learning framework for evaluating geomagnetic storm effects on MisrSat2 satellite power subsystems. [PDF]

Sci Rep
Mostafa MS, Ali MAB, Hesham N, Yassin YM, Ahmed A, Elfiky D.   +5 more
europepmc   +1 more source

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Single Event Upset at Ground Level

IEEE Transactions on Nuclear Science, 1996
Ground level upsets have been observed in computer systems containing large amounts of random access memory (RAM). Atmospheric neutrons are most likely the major cause of the upsets based on measured data using the Weapons Neutron Research (WNR) neutron beam.
E Normand
exaly   +2 more sources

Laser Simulation of Single Event Upsets

IEEE Transactions on Nuclear Science, 1987
A pulsed picosecond laser was used to produce upsets in both a commercial bipolar logic circuit and a specially designed CMOS SRAM test structure. Comparing the laser energy necessary for producing upsets in transistors that have different upset sensitivities with the single event upset (SEU) level predicted from circuit analysis showed that a ...
S P Büchner, A R Knudson, A B Campbell
exaly   +2 more sources

Single event upset mitigation for FDP2008

2011 9th IEEE International Conference on ASIC, 2011
Highly integrated contemporary SRAM-based Field Programmable Gate Arrays (FPGAs) lead to high occurrence-rate of transient faults induced by Single Event Upsets (SEUs) in FPGAs' configuration memory. In this paper, Fudan Design Environment (FDE) Triple Module Redundancy (TMR) approach for design triplication has been devised to meet high-reliability ...
Meng Yang, Gengsheng Chen
openaire   +1 more source

A Single Event Upset Resilient Latch Design with Single Node Upset Immunity

Journal of Electronic Testing, 2019
In this paper, a latch design with single node immunity to single event upsets during the hold state is proposed. This structure is based on the original Quatro latch and have two more redundant storage nodes. Compared with the reference, this structure is able to recover if any of these nodes is struck by ion particles during the hold state and it ...
Xixi Dai, Haibin Wang, Jiamin Chu, Zhi Liu 0004, Li Cai, Kang Yan   +5 more
openaire   +1 more source