Results 221 to 230 of about 1,939,285 (262)

A Ultra-Low Specific On-Resistance and Extended Gate SJ LDMOS Structure

Transactions on Electrical and Electronic Materials, 2021
A new structure of extended gate (EG) SJ LDMOS is proposed in this paper to overcome the substrate assisted depletion (SAD) effect in the structure of Super-Junction lateral double diffused metal oxide semiconductor (SJ LDMOS). Different from other surface SJ structures, the SJ layer of the structure is located in the body of the drift region.
Lijuan Wu, Jiaqi Chen, Hang Yang, QiLin Ding, Xing Chen, Shaolian Su   +5 more
openaire   +1 more source

Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

Journal of Semiconductors, 2011
An ultra-low specific on-resistance ( R on,sp ) silicon-on-insulator (SOI) double-gate trench-type MOSFET (DG trench MOSFET) is proposed. The MOSFET features double gates and an oxide trench: the oxide trench is in the drift region, one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide.
Tianfei Lei, Xiaorong Luo, Rui Ge, Xi Chen, Yuangang Wang, Guoliang Yao, Yongheng Jiang, Bo Zhang, Zhaoji Li   +8 more
openaire   +1 more source

A 700 V low specific on-resistance self-isolated DB-nLDMOS

2014 IEEE International Conference on Electron Devices and Solid-State Circuits, 2014
A 700 V self-ISO (isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) without epitaxy is proposed in this paper. By separately implanting deep junction NWELLs, drift region of low doping concentration in neck region is achieved. This alleviates the concentration of the electric field and avoids premature avalanche breakdown around the bird's beak ...
null Kun Mao, null Ming Qiao, null Wentong Zhang, null Zhaoji Li, null Bo Zhang   +4 more
openaire   +1 more source

Accumulation-mode high voltage SOI LDMOS with ultralow specific on-resistance

2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2015
A high breakdown voltage (BV) thin SOI LDMOS with ultralow specific on-resistance is proposed and its mechanism is investigated. The LDMOS features an accumulation-mode extended gate (AEG) structure on the surface that consists of a P- region and two diodes in series. In the on-state, an electron accumulation layer is formed at the drift region surface
Jie Wei, Xiaorong Luo, Yanhui Zhang, Pengcheng Li, Kun Zhou, Zhaoji Li, Dameng Lei, Fanzhou He, Bo Zhang   +8 more
openaire   +1 more source

Optimization of Lateral Superjunction Based on the Minimum Specific ON-Resistance

IEEE Transactions on Electron Devices, 2016
The optimization methodology of the minimum specific ON-resistance $R_{\mathrm{\scriptscriptstyle ON},\textrm {min}}$ for the lateral superjunction device is proposed based on the concepts of charge and potential electric fields in this paper. From the $R_{\mathrm{\scriptscriptstyle ON},\textrm {min}}$ method, a new relationship between $
Wentong Zhang, Bo Zhang, Ming Qiao, Zehong Li, Xiaorong Luo, Zhaoji Li   +5 more
openaire   +1 more source

Numerical analysis of specific on-resistance for trench gate superjunction MOSFETs

Japanese Journal of Applied Physics, 2015
The numerical analysis results and theoretical limit of specific on-resistance (RON·A) for a parallel trench gate superjunction (SJ) MOSFET where a striped trench gate structure is parallel to a striped SJ structure and a perpendicular trench gate SJ-MOSFET where the striped trench gate structure is perpendicular to the striped SJ structure are ...
Yasuhiko Onishi, Yoshio Hashimoto
openaire   +1 more source

A very low specific on-resistance high-voltage SOI lateral MOSFET

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, 2012
A silicon-on-insulator buried layer multiple trenches (SOI BMT) metal-oxide-semiconductor-field-effect -transistor (MOSFET) with very low specific on-resistance (R on, sp ) is proposed in this paper. Based on the research of the SOI multiple trenches MOSFET (SOI MT MOSFET) with low R on, sp , an P-type buried layer is introduced on top of the BOX in ...
Zhi Zheng, Wei Li, Hui Li, Ping Li
openaire   +1 more source

Optimization of the specific on-resistance of the COOLMOS/sup TM/

IEEE Transactions on Electron Devices, 2001
The optimized values for the physical and geometrical parameters of the p- and n-regions used in the voltage-sustaining layer of the COOLMOS/sup TM/ are presented. Design of the parameters is aimed to produce the lowest specific on-resistance, R/sub on/ for a given breakdown voltage, V/sub B/.
null Xing-Bi Chen, J.K.O. Sin
openaire   +1 more source

250V Integrable Silicon Lateral Trench Power MOSFETs with Superior Specific On-Resistance

Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC's, 2007
A lateral trench power MOSFET in the 250 V class, with a reduced specific on-resistance is proposed. Simulation results of an optimized device structure exhibits a low specific on-resistance of 7 mOmega -cm2, which is 2.5times lower than that of the conventional lateral DMOSFET. Effects of design parameters on the device performance are examined.
K.R. Varadarajan, T.P. Chow, J. Wang, R. Liu, F. Gonzalez   +4 more
openaire   +1 more source

Enhancement-mode GaN HEMT power electronic device with low specific on resistance

2017 14th China International Forum on Solid State Lighting: International Forum on Wide Bandgap Semiconductors China (SSLChina: IFWS), 2017
An enhancement-mode GaN HEMT on silicon substrate was obtained by using p-type GaN Cap. P-type GaN cap was obtained by Mg doping. The activation concentration of the p-GaN cap was 3e17cm−3 with a thickness of 60nm. Selective dry etching was used to fabricate the device. Back metal and substrate thinning was used for improving the cooling capacity.
Kong Cen, Zhou Jianjun, Kong Yuechan, Zhang Kai, Chen Tangsheng   +4 more
openaire   +1 more source