Results 1 to 10 of about 236 (173)

A hybrid VIGBT-LDMOS transistor

IEEE Transactions on Electron Devices, 1988
A hybrid VIGBT-LDMOS transistor which consists of a VIGBT (vertical insulated-gate bipolar transistor) path with a lateral DMOSFET path, implemented in a 300-V, p-channel version, has been demonstrated. The device can be operated with series resistors attached to either the collector or the drain terminals.
T.P. Chow, B.J. Baliga
openaire   +1 more source

An Application of LDMOS on ESD Protection

2020 China Semiconductor Technology International Conference (CSTIC), 2020
This paper focuses on the application of a LDMOS ESD protection method. The application is by tuning the size of poly cover field oxide. It needn't extra process step. This way can reduce the breakdown voltage. When ESD is coming, this device can turn on first, then protect the core the Chip.
Li Wang, Yu Chen, Hualun Chen
openaire   +1 more source

Hot carrier reliability in LDMOS devices

2017 IEEE 12th International Conference on ASIC (ASICON), 2017
This paper discusses hot carrier (HC) reliability in LDMOS devices. First we review various HC degradation mechanisms for LDMOS devices. Then we discuss how to reduce HC degradation in LDMOS devices.
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A Review of Super Junction LDMOS

IETE Technical Review, 2011
AbstractSuper Junction Lateral Double-diffused MOSFET (SJ-LDMOS) is one of the important attractive devices in high-voltage integrated circuit and power integrated circuit. However, the SJ-LDMOS is generally implemented on a low-resistance substrate, which always suffers from substrate-assisted depletion (SAD) effect, which thus degrades the ...
Chen Hu, Xiaoying He, Ming Li, Weifeng Sun   +3 more
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Design a reliable LDMOS module for aonic application

ICMMT 4th International Conference on, Proceedings Microwave and Millimeter Wave Technology, 2004., 2005
This paper describes a design technique of LDMOS module for avionics and military application. These techniques are particularly oriented in theories and computer aided design. We introduce a practical external matching network design topology to achieve a smaller physical size using microstrip line. The circuit analysis used both transmission line and
null Cang Nguyen, L. He
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Improvement of LDMOS MMICs compactness

2016 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications (PAWR), 2016
This paper describes an innovative mean of realizing input matching networks for LDMOS MMICs, by using a very compact broadband transformer balun, which is integrated in the input matching network, in the active device gate plane instead of the 50 ohms port.
Sullivan Plet, Gerard Bouisse, Michel Campovecchio   +2 more
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Study of the power capability of LDMOS and the improved methods

Microelectronics Reliability, 2006
In this paper, the failure process of LDMOS is analyzed. It is found that three peak electric fields locate in the Si/SiO2 interface of LDMOS, which result in three hot spots. From the time the device turns on, the first peak electric field increases and the second one remains constant while the third one decreases.
Zhilin Sun, Weifeng Sun 0001, Yangbo Yi, Longxing Shi   +3 more
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A novel trench gate LDMOS

2003 International Semiconductor Conference. CAS 2003 Proceedings (IEEE Cat. No.03TH8676), 2004
In this paper a novel trench gate lateral double diffused MOSFET (TG-LDMOS) device will be discussed and compared to the conventional LDMOS structure. Currently, the LDMOS devices are the preferred technology for base station amplifiers and in Power MOSFET switching applications.
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A high-voltage p-LDMOS with enhanced current capability comparable to double RESURF n-LDMOS

2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2018
In this paper, a simple p-LDMOS structure with significantly improved performances based on a novel three dimensional concept is proposed. The hole current in the Ptop region of the signal region flows into the floating P+, then through the integrated resistor R p formed by the Pbase region in the z-axis direction with a distance of W 2 +W 3 , into ...
Bo Yi, Junji Cheng, Moufu Kong, Bingke Zhang, Xing Bi Chen   +4 more
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120 V interdigitated-drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limit

IEEE Transactions on Electron Devices, 2000
A new device structure named IDLDMOS is proposed to overcome the power LDMOS limit (R/sub on, sp/ /spl prop/ BV/sub dss//sup 2.5/). The concept is based on replacing LDMOS lightly doped n-drift region by moderately doped alternating p and n layers of suitable dimension and doping.
Xu, S., Gan, K.P., Samudra, G.S., Liang, Y.C., Sin, J.K.O.   +4 more
openaire   +2 more sources