Results 31 to 40 of about 1,991 (213)
Superjunction LDMOS With Dual Gate for Low On-Resistance and High Transconductance
IEEE Journal of the Electron Devices Society, 2020 In this paper, a novel bulk silicon lateral superjunction double diffused MOSFET (SJ-LDMOS) with dual gate (DG) is proposed and its mechanism is investigated by numerical TCAD simulations.
Zhen Cao, Licheng Jiao
doaj +1 more source
IEEE Journal of the Electron Devices Society, 2022 An ultra-low specific on-resistance 4H-SiC power laterally diffused metal oxide semiconductor (LDMOS) device is proposed for 1200V-class applications.
Moufu Kong +5 more
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A reduced-size branch-line coupler for improved LDMOS balanced power amplifiers [PDF]
, 2009 This article discusses the application of a reduced-size branch-line coupler in the design of a LDMOS class-AB balanced power amplifier at a center frequency of 2.14 GHz.
Budimir, D. +2 more
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LDMOS Drift Region With Field Oxides: Figure-of-Merit Derivation and Verification
IEEE Journal of the Electron Devices Society, 2022 We analytically and numerically investigate the performance of Laterally-Diffused Metal-Oxide-Semiconductor (LDMOS) transistors with Semi-circular Field OXide (S-FOX) focusing on mid-voltage (30 V – 100 V) power applications.
Ali Saadat +3 more
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Hot-Carrier-Induced Reliability for Lateral DMOS Transistors With Split-STI Structures
IEEE Journal of the Electron Devices Society, 2021 In this work, four kinds of lateral double-diffused MOS (LDMOS) devices with different split shallow trench isolation (STI) structures (Device A: LDMOS with traditional split-STI, Device B: LDMOS with slope-STI, Device C with step-STI and Device D with H-
Li Lu +7 more
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A Zero-Cost Technique to Improve ON-State Performance and Reliability of Power LDMOS Transistors
IEEE Journal of the Electron Devices Society, 2021 In this paper, we have proposed a simple and zero-cost technique to improve ON-state and reliability performance of LDMOS transistors. We introduced doping gradient in the channel by optimizing position of the P-Well mask during test structure design ...
Kumari Neeraj Kaushal +1 more
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On the modeling of LDMOS RF power transistors
IEEE Custom Integrated Circuits Conference 2010, 2010 In this review we present a technology-independent approach to the construction of a circuit model for a high-power radio-frequency (RF) LDMOS FET. We compare and contrast this approach with other MOSFET modeling approaches used for digital and RF CMOS applications.
John Wood, Peter H. Aaen
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AIP Advances, 2017 The use of contact etching stop layer (CESL) stressors is a popular technique for introducing stress into a transistor channel. However, when tensile stress is applied to an n-type lateral double-diffused metal-oxide-semiconductor ...
Xiangzhan Wang +5 more
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LDMOS RF power amplifiers with improved performance characteristics using defected ground structure [PDF]
, 2006 An LDMOS RF power amplifier with improved performance characteristics such as intermodulation distortion (IMD) and power-added efficiency (PAE) using a defected ground structure (DGS) matching circuit and bias lines is presented.
Budimir, D., Koulouzis, H.
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3D RESURF Effect For LDMOS Devices [PDF]
, 2009 [[abstract]]In recent years, the power devices become more and more important due to the big demands for liquid crystal display (LCD), electrical plasma display, LED, and communication products.
Chin-Che Lin
core +2 more sources