Results 171 to 180 of about 37,708 (227)

Defect tolerant SRAM based FPGAs

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2002
We propose a new approach to redundancy for field programmable gate arrays (FPGAs) which uses a novel reconfiguration network. Modifications are made to the wiring segments and a spare element is incorporated at the end of each row. By using the technique it will be possible to construct arrays 10 times larger than are commercially economic at present.
Jason L. Kelly, Peter A. Ivey
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A fault injection tool for SRAM-based FPGAs

9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., 2004
A fault injection tool for SRAM-based FPGAs based on the fault emulation technique is presented. Faults are injected by modifying the configuration bitstream while this is loaded into the device, without using standard synthesis tools or available commercial software, such as Jbits or similar.
Monica Alderighi, Sergio D'Angelo, Marcello Mancini, Giacomo R. Sechi   +3 more
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An SRAM-based FPGA architecture

Proceedings of Custom Integrated Circuits Conference, 2002
An SRAM-based FPGA architecture has been developed using a licensed AT6000 architecture base. The logic-cell architecture exploits an efficient, medium-grained, fixed library cell that implements most frequently used synthesis functions. An internal routing structure enables dense designs using a highly connected grid-based routing system and a ...
S. Gould, B. Worth, K. Clinton, E. Millham, F. Keyser, R. Palmer, S. Hartman, T. Zittritsch   +7 more
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On the reliability evaluation of sram-based FPGA designs

International Conference on Field Programmable Logic and Applications, 2005., 2005
Benefits of field programmable gate arrays (FPGAs) have lead to a spectrum of use ranging from consumer products to astronautics. This diversity necessitates the need to evaluate the reliability of the FPGA, because of their high susceptibility to soft errors, which are due to the high density of embedded SRAM cells.
Olivier Héron, Talal Arnaout, Hans-Joachim Wunderlich   +2 more
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An automated test framework for SRAM-based FPGA

2015 IEEE 11th International Conference on ASIC (ASICON), 2015
An automated test framework for SRAM-based FPGA is presented. With the framework, test configurations of different categories can be partially or completely generated, and the tests be running using the generated configurations. Data driven design provides the test framework the flexibility of change the user interface and the command line arguments ...
Xuemin Lv, Moucheng Yang, Xuegong Zhou, Lingli Wang   +3 more
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On the Static Cross Section of SRAM-Based FPGAs

2008 IEEE Radiation Effects Data Workshop, 2008
We present new experimental results about the sensitivity of SRAM-based FPGAs to heavy ions. We analyze the static cross section as a function of the FPGA resource type. We also study the soft error rate as function of the accumulated total dose, and investigate the occurrence of multiple bit upsets in the configuration memory.
MANUZZATO, ANDREA, GERARDIN, SIMONE, PACCAGNELLA, ALESSANDRO, Sterpone, L., Violante, M.   +4 more
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A diagnosis method for interconnects in SRAM based FPGAs

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259), 2002
This paper presents a five-step programming method to diagnose faults in FPGA interconnection resources. A single and a multiple fault model are given. The accuracy of fault location is a single segment for a segment stuck-at fault or a segment open fault, a segment pair or terminal pair for bridge fault or switch stuck-off fault under the single fault
Yinlei Yu, Jian Xu, Wei-Kang Huang, Fabrizio Lombardi   +3 more
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Power Optimization Techniques for SRAM-Based FPGAs

2006 International Conference on Field Programmable Logic and Applications, 2006
In this work, the authors aim to improve the power efficiency of FPGAs by proposing two power reduction techniques: the authors present a low-penalty optimization technique to reduce leakage power consumption in FPGA logic blocks by exploiting the variance in LUT utilization across different designs (Mondal and Memik, (2005)), and presents a dual-Vdd ...
Somsubhra Mondal, Seda Ogrenci Memik
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Power estimation approach for SRAM-based FPGAs

Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, 2000
This paper presents the power consumption estimation for the novel Virtex architecture. Due to the fact that the XC4000 and the Virtex core architecture are very similar, we used the basic approaches for the XC4000-FPGAs power consumption estimation and extended that method for the new Virtex family.
Karlheinz Weiß, Carsten Oetker, Igor Katchan, Thorsten Steckstor, Wolfgang Rosenstiel   +4 more
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Reconfigurable Fault Tolerant Processor on a SRAM based FPGA

2020 IEEE International Conference on Electro Information Technology (EIT), 2020
The hardware of the satellite system is mission-critical of the whole system. The commercial off-the-shelf (COTS) components are commonly used in satellite systems due to their low cost. They are not hardened to withstand the space-born radiation, and thus, may fail, jeopardizing the entire mission.
Bhargav Shashidhara, Shrikant Jadhav, Youngsoo Kim 0001   +2 more
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