Results 191 to 200 of about 37,708 (227)

Cost-efficient of a cluster in a mesh SRAM-based FPGA

2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 2014
This paper presents a cost-efficient Built-In Self-Test (BIST) scheme for fault detection and diagnosis of a cluster in a mesh FPGA. In this scheme, test cost reduction is achieved by simultaneous testing of logic and intra-cluster interconnect resources without degradation of diagnostic resolution.
Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel   +2 more
openaire   +1 more source

Testing the Local Interconnect Resources of SRAM-Based FPGA's

Journal of Electronic Testing, 2000
This paper addresses the problem of testing the configurable modules used in the local interconnect of SRAM-based FPGAs. First, it is demonstrated that a n address bit Configurable Interface Multiplexer requires N e 2n test configurations considering a stuck-at as well as a functional fault model. Second, a logic cell with a set of k input Configurable
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian   +3 more
openaire   +1 more source

Designing fault tolerant systems into SRAM-based FPGAs

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451), 2003
This paper discusses high level techniques for designing fault tolerant systems in SRAM-based FPGAs, without modification in the FPGA architecture. Triple Modular Redundancy (TMR) has been successfully applied in FPGAs to mitigate transient faults, which are likely to occur in space applications.
Fernanda Lima 0001, Luigi Carro, Ricardo Augusto da Luz Reis   +2 more
openaire   +1 more source

Self rerouting of dynamically reconfigurable SRAM-based FPGAs

2017 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2017
Reconfigurable devices are widely attractive for several application fields thanks to their size, rapid prototyping characteristics, flexibility and upgradability. Thanks to partial Reconfiguration features, FPGA becomes the golden core of the adaptive computation paradigm since they may dynamically change their functionalities based on the elaboration
BOZZOLI, LUDOVICA, STERPONE, LUCA
openaire   +2 more sources

Criticality-aware scrubbing mechanism for SRAM-based FPGAs

2014 24th International Conference on Field Programmable Logic and Applications (FPL), 2014
Scrubbing has been considered as an effective mechanism to provide fault-tolerance in Static-RAM (SRAM)-based Field Programmable Gate Arrays (FPGAs). However, the current scrubbing techniques execute without considering the criticality and timing of the user tasks implemented in the FPGA.
Rui Santos, Shyamsundar Venkataraman, Anup Das 0001, Akash Kumar 0001   +3 more
openaire   +1 more source

An analytical delay model for SRAM-based FPGA interconnections

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198), 1999
In an SRAM-based FPGA, MOS transistors connect wire segments to construct interconnections between CLBs, resulting in large and unpredictable path delays. So it is necessary to be able to estimate interconnection delays quickly and accurately in order that performance-driven layout and analysis algorithms can achieve high quality. Because the effective
Feng Zhou, Zhijun Huang, Jiarong Tong, Pushan Tang   +3 more
openaire   +1 more source

SRAM-Based FPGAs: Testing the Embedded RAM Modules

Journal of Electronic Testing, 1999
This paper addresses the problem of testing the RAM mode of the LUT/RAM modules of configurable SRAM-based Field Programmable Gate Arrays (FPGAs) using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2N memory cells is proposed taking into account the LUT and RAM modes.
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian   +3 more
openaire   +1 more source

A Flexible Inexact TMR Technique for SRAM-based FPGAs

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016
Single Event Upsets (SEUs) inadvertently change the logic memory and thereby the configuration of the Field Programmable Gate Arrays (FPGAs), leading to their incorrect functioning. Traditional methods to tolerate such faults include Triple Modular Redundancy (TMR). However, such method has a high overhead in terms of power and area.
Shyamsundar Venkataraman, Rui Santos, Akash Kumar 0001   +2 more
openaire   +2 more sources

Reliability of a softcore processor in a commercial SRAM-based FPGA

Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, 2012
Softcore processors are an attractive alternative to using radiation-hardened processors in space-based applications. Unlike traditional processors however, the logic and routing of a softcore processor are vulnerable to the effects of single-event upsets (SEUs).
Nathaniel H. Rollins, Michael J. Wirthlin   +1 more
openaire   +1 more source

SRAM-based FPGA's: testing the interconnect/logic interface

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259), 2002
This paper address the problem of testing the configurable modules that interface the global interconnect and the logic cells of SRAM-based FPGAs. The Configurable Interface Modules (CIMs) are assumed to be implemented with FPGA multiplexers but the results can be easily extended to any type of interface module.
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian   +3 more
openaire   +1 more source