Results 181 to 190 of about 37,708 (227)

An XDL Analysis Method for SRAM-Based FPGA

2016
Soft errors due to single event upsets (SEUs) are the main challenge to the reliability of SRAM-based FPGA designs. To calculate the soft error rate, the XDL information, such as the sensitive configuration bits, signal propagation, is needed to be acquired. In this paper, an XDL analysis method for SRAM-based FPGA is presented.
Junfeng Liu, Yunyi Yan, Jinfu Wu
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Analyzing SEU effects is SRAM-based FPGAsb

9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., 2003
Commercial-off-the-shelf SRAM-based FPGA devices are becoming of interests for applications where high dependability and low cost are mandatory constraints. This paper proposes a new method for assessing the effects of SEUs in the device configuration memory.
VIOLANTE, MASSIMO, CESCHIA, M., SONZA REORDA, Matteo, PACCAGNELLA, A., BERNARDI, PAOLO, REBAUDENGO, Maurizio, BORTOLATO, D., BELLATO, M., ZAMBOLIN, P., CANDELORI, A.   +9 more
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Efficient estimation of SEU effects in SRAM-based FPGAs

11th IEEE International On-Line Testing Symposium, 2005
SRAM-based FPGAs are becoming very appealing for several applications where high dependability is a mandatory requirement. Unfortunately, the technology of SRAM-based FPGAs is very sensitive to single event upsets (SEUs) and particular concerns arise from SEUs affecting the FPGAs' configuration memory.
SONZA REORDA, Matteo, STERPONE, Luca, VIOLANTE, MASSIMO   +2 more
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Testing embedded RAM modules in SRAM-based FPGAs

Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, 2006
This paper presents a unique scheme for testing and locating multiple stuck at faults in the embedded RAM modules of SRAM-based FPGAs. The RAM modules are tested using the MATS++ algorithm. The interconnection scheme makes it possible to test all the cells within the RAM modules in the FPGA in just one test configuration.
Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali   +2 more
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Evaluation of fault attack detection on SRAM-based FPGAs

2017 18th IEEE Latin American Test Symposium (LATS), 2017
In this paper we present an extended fault injection approach to configuration memory of SRAM-based FPGAs consisting of inter frame many bits upsets to be used as an evaluation tool for attack detection capability and countermeasure effectiveness in security sensitive design modules. The work presented in this paper is twofold.
Fabio Benevenuti, Fernanda Lima Kastensmidt   +1 more
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Dependability issues in SRAM-based FPGA design

2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007
- tutorial a la conference qui a eu lieu en Decembre 2007 a Marrakech, Maroc, sur le theme "".
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SRAM-based FPGA's: testing the LUT/RAM modules

Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), 2002
This paper addresses the problem of testing the LUT/RAM modules of configurable SRAM-based FPGAs using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2/sup N/ memory cells is proposed taking into account the LUT and RAM modes.
Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian   +3 more
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A novel fault tolerant approach for SRAM-based FPGAs

Proceedings 1999 Pacific Rim International Symposium on Dependable Computing, 2003
This paper presents a novel fault tolerant approach for SRAM-based FPGAs. The proposed approach includes a fault tolerant architecture and its related routing procedure. In the approach, both the overheads for CLBs and interconnects are considered. The fault tolerant routing procedure under this novel approach is simple and less time-consuming.
Jian Xu, Paifa Si, Wei-Kang Huang, Fabrizio Lombardi   +3 more
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Testing carry logic modules of SRAM-based FPGAs

Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing, 2002
The carry logic module (CLM) is an integral part of a configurable logic block (CLB) in a Xilinx XC4000 field programmable gate array (FPGA). This paper addresses the testing issues of a CLM for the first time. The integrity of a CLM is validated by the integrity of all its components.
Xiaoling Sun, Jian Xu, Pieter M. Trouborst   +2 more
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Diagnosing single faults for interconnects in SRAM based FPGAs

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198), 1999
This paper presents a method to diagnose faults in FPGA interconnection resources. A single fault model is given. Under the given model, a diagnosing method is proposed. At most five programming steps in the proposed method is required if adaptive testing scheme is used.
Yinlei Yu, Jian Xu, Wei-Kang Huang, Fabrizio Lombardi   +3 more
openaire   +1 more source