Results 151 to 160 of about 55,126 (212)
Temperature Gradients as a Data Storage Principle. [PDF]
Entropy (Basel)Schoenmaker J, Martins PG, Teixeira JC.
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Concealable physical unclonable functions using vertical NAND flash memory. [PDF]
Nat CommunPark SH +5 more
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SRAM Gauge: SRAM Health Monitoring via Cells Race
2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2021By shrinking transistors' dimensions and, consequently, reducing the operating voltage in nano-scale CMOS technologies, the stability of SRAM cells has become a major reliability concern. SRAM cells' robustness against undesirable bit-flips is commonly measured by Static Noise Margin (SNM). Degradation in SNM is mainly because of the gradual variations
Nezam Rohbani, Masoumeh Ebrahimi
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2021 XXXVI Conference on Design of Circuits and Integrated Systems (DCIS), 2021
As technology advances and becomes increasingly smaller in scale, it makes performance and reliability a constant problem. Effects such as process variations (P), power-supply voltage variations (V), temperature variations (T) and aging (A) variations (PVTA - Process, Voltage, Temperature and Aging) are key parameters that affect circuit's performance ...
Jorge Semião +2 more
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As technology advances and becomes increasingly smaller in scale, it makes performance and reliability a constant problem. Effects such as process variations (P), power-supply voltage variations (V), temperature variations (T) and aging (A) variations (PVTA - Process, Voltage, Temperature and Aging) are key parameters that affect circuit's performance ...
Jorge Semião +2 more
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Proceedings of the 2019 Great Lakes Symposium on VLSI, 2019
We present an in-memory computing SRAM macro for binary neural networks. The memory macro computes XNOR-and-accumulate for binary/ternary deep convolutional neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay-product than digital ASIC and achieves high accuracy in machine learning ...
Zhewei Jiang +3 more
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We present an in-memory computing SRAM macro for binary neural networks. The memory macro computes XNOR-and-accumulate for binary/ternary deep convolutional neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay-product than digital ASIC and achieves high accuracy in machine learning ...
Zhewei Jiang +3 more
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NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors
IEEE Journal of Solid-State Circuits, 2001This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatile SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the ...
T. Miwa +9 more
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Carbon Nanotube-Based CMOS SRAM: 1 kbit 6T SRAM Arrays and 10T SRAM Cells
IEEE Transactions on Electron Devices, 2019We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). We demonstrate 1 kbit (1024) 6 transistor (6T) SRAM arrays fabricated with complementary metal-oxide-semiconductor (CMOS) CNFETs (totaling 6144 p- and n-type CNFETs), with all 1024 cells functioning ...
Pritpal S. Kanhaiya +4 more
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Yield estimation of SRAM circuits using "Virtual SRAM Fab"
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009Static Random Access Memories (SRAMs) are key components of modern VLSI designs and a major bottleneck to technology scaling as they use the smallest size devices with high sensitivity to manufacturing details. Analysis performed at the "schematic" level can be deceiving as it ignores the interdependence between the implementation layout and the ...
Aditya Bansal +11 more
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Proceedings of the IEEE, 1999
This paper describes a new high-density low-power circuit approach for implementing static random access memory (SRAM) using low current density resonant tunneling diodes (RTDs). After an overview of semiconductor random access memory architecture and technology, the concept of tunneling-based SRAM (TSRAM) is introduced.
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This paper describes a new high-density low-power circuit approach for implementing static random access memory (SRAM) using low current density resonant tunneling diodes (RTDs). After an overview of semiconductor random access memory architecture and technology, the concept of tunneling-based SRAM (TSRAM) is introduced.
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