Results 171 to 180 of about 13,883 (233)
Bi-Directional and Operand-Controllable In-Memory Computing for Boolean Logic and Search Operations with Row and Column Directional SRAM (RC-SRAM). [PDF]
Micromachines (Basel)Xiao H, Zhao R, Liu Y, Liu Y, Chen J.
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Sex-Specific Formation of 1,2:3,4-Diepoxybutane-Derived Hemoglobin Adducts in 1,3-Butadiene-Exposed Workers. [PDF]
Chem Res ToxicolGeorgieva NI +7 more
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Validation of Inertial Sensor-Based Step Detection Algorithms for Edge Device Deployment. [PDF]
Sensors (Basel)Kisiel M, Amjad A, Szczęsna A.
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SRAM Gauge: SRAM Health Monitoring via Cells Race [PDF]
2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2021 By shrinking transistors' dimensions and, consequently, reducing the operating voltage in nano-scale CMOS technologies, the stability of SRAM cells has become a major reliability concern. SRAM cells' robustness against undesirable bit-flips is commonly measured by Static Noise Margin (SNM). Degradation in SNM is mainly because of the gradual variations
Nezam Rohbani, Masoumeh Ebrahimi
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NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors
IEEE Journal of Solid-State Circuits, 2001This paper demonstrates new circuit technologies that enable a 0.25-/spl mu/m ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatile SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the ...
H Hada, T Kunio, H Toyoshima
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Carbon Nanotube-Based CMOS SRAM: 1 kbit 6T SRAM Arrays and 10T SRAM Cells
IEEE Transactions on Electron Devices, 2019We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). We demonstrate 1 kbit (1024) 6 transistor (6T) SRAM arrays fabricated with complementary metal-oxide-semiconductor (CMOS) CNFETs (totaling 6144 p- and n-type CNFETs), with all 1024 cells functioning ...
Mindy Bishop +2 more
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Junctionless 6T SRAM cell [PDF]
Electronics Letters, 2010 The design of a 6T SRAM cell with 20 nm junctionless (JL) MOSFETs is reported. It is shown that a 6T SRAM cell designed with JL MOSFETs achieves a high static noise margin (SNM) of 185 mV, retention noise or hold margin (RNM) of 381 mV and writability ...
P Razavi, J -P Colinge, I Ferain
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2011 International Symposium on Electronic System Design, 2011
In this paper an effort is made to design an energy efficient 5T SRAM in 65nm technology. The energy recovery driver saves energy in the single bit line in addition to enhancing the write ability of the 5T SRAM. The energy recovery is possible by pumping the bit line energy back into the bit line voltage source instead of allowing to ground after write
Mamatha Samson, Satyam Mandavalli
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In this paper an effort is made to design an energy efficient 5T SRAM in 65nm technology. The energy recovery driver saves energy in the single bit line in addition to enhancing the write ability of the 5T SRAM. The energy recovery is possible by pumping the bit line energy back into the bit line voltage source instead of allowing to ground after write
Mamatha Samson, Satyam Mandavalli
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2011 5th International Conference on Network and System Security, 2011
Key storage is a well-known security issue. Usually, keys are generated and then stored in an non-volatile memory (NVM). A promising alternative are the so-called physical unclonable functions (PUFs). These functions extract key material directly from manufacturing variabilities of a device. One example of such a PUF is the SRAM-PUF.
Christoph Böhm 0003 +2 more
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Key storage is a well-known security issue. Usually, keys are generated and then stored in an non-volatile memory (NVM). A promising alternative are the so-called physical unclonable functions (PUFs). These functions extract key material directly from manufacturing variabilities of a device. One example of such a PUF is the SRAM-PUF.
Christoph Böhm 0003 +2 more
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Proceedings of the IEEE, 1999
This paper describes a new high-density low-power circuit approach for implementing static random access memory (SRAM) using low current density resonant tunneling diodes (RTDs). After an overview of semiconductor random access memory architecture and technology, the concept of tunneling-based SRAM (TSRAM) is introduced.
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This paper describes a new high-density low-power circuit approach for implementing static random access memory (SRAM) using low current density resonant tunneling diodes (RTDs). After an overview of semiconductor random access memory architecture and technology, the concept of tunneling-based SRAM (TSRAM) is introduced.
openaire +1 more source