Results 171 to 180 of about 55,876 (211)

A Supply Fluctuation Resilient SRAM

2018 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
This paper presents a novel SRAM architecture that holds the data when the supply voltage is disrupted or lost for about one second. This SRAM architecture introduces a new category of memories that are resilient to supply fluctuations. This can be beneficial in many applications that rely on power harvesting to operate.
Sepideh Nouri, Joseph R. Cavallaro
openaire   +1 more source

FinFET-based SRAM design

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005., 2005
Intrinsic variations and challenging leakage control in today's bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRAM cells are presented in this work. It is found that 6-T and 4-T FinFET-based SRAM cells designed with built-in feedback achieve significant improvements in the cell static ...
Zheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King 0001, Borivoje Nikolic   +4 more
openaire   +1 more source

Design and test of an SRAM chip

2013 IEEE 10th International Conference on ASIC, 2013
A fully customized 8×8 bits SRAM chip, based on Chartered 0.35 um EEPROM CMOS technology, is designed and taped-out for low-power and low-cost electronic equipment. According to test results, when the supply voltage is 3.3 V and clock frequency is 20 MHz, the chip can work correctly, and the performance reaches the design specifications, the access ...
Wenbin Liu, Jinhui Wang, Ligang Hou, Hongyan Yang, Jianbo Kang   +4 more
openaire   +1 more source

SEU tolerant SRAM cell

2011 12th International Symposium on Quality Electronic Design, 2011
Modern integrated circuits require careful attention to the soft errors resulting into bit upsets, which are normally caused by alpha particle or neutron hits. These events, also referred to as single-event upsets (SEUs), will become more severe for future technologies. In this paper we propose a novel 10T SEU tolerant SRAM cell design.
Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita   +4 more
openaire   +1 more source

FinFET SRAM design challenges

2014 IEEE International Conference on IC Design & Technology, 2014
The utilization of FinFET devices in the SRAM cell provides many benefits over planar bulk devices due to the fully-depleted behavior with improved subthreshold slope, short-channel effects, drive current, and mismatch. However, the quantized nature of the fins results in several new challenges as compared to planar devices.
David Burnett, Sanjay Parihar, Hema Ramamurthy, Sriram Balasubramanian   +3 more
openaire   +1 more source

Reliability Enhancement of CMOS SRAMs

2005 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT'05), 2005
Gate-oxide defect is the major cause of the reliability problems for CMOS ICs. The common practice for reliability enhancement is the use of extreme-voltage screening and then the high-temperature burn-in screening, where the Iddq-test approach is generally used to generate the stress vectors for the extreme-voltage screening.
Chin-Long Wey, Meng-Yao Liu, Shaolei Quan   +2 more
openaire   +1 more source

Introduction to SRAM

2012
The trend of Static Random Access Memory (SRAM) along with CMOS technology scaling in different processors and system-on-chip (SoC) products has fuelled the need of innovation in the area of SRAM design. SRAM bitcells are made of minimum geometry devices for high density and to keep the pace with CMOS technology scaling, as a result, they are the first
Jawar Singh, Saraju P. Mohanty, Dhiraj K. Pradhan   +2 more
openaire   +1 more source

SRAM Vmax stability considerations

2015 IEEE International Reliability Physics Symposium, 2015
The voltage overdrive of SRAM cells is shown to be of concern as the stability at Vmax can be worse than at Vmin. The Vmax stability is especially sensitive to high resistances on single devices in the bitcell. Highlighted in this paper are SRAM Vmax stability issues observed in a 28nm technology as well as the increased susceptibility of FinFET SRAM ...
David Burnett, Sriram Balasubramanian, Vivek Joshi, Sanjay Parihar, Jack M. Higman, C. Weintraub   +5 more
openaire   +1 more source

Ultralow-power SRAM technology

IBM Journal of Research and Development, 2003
An ultralow-standby-power technology has been developed in both 0.18-µm and 0.13-µm lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage six-transistor (6T) SRAM cell sizes are 4.81 µm2 and 2.34 µm2, corresponding respectively to the 0.18-µm and 0.13-µm design dimensions.
Randy W. Mann, W. W. (Bill) Abadeer, Matthew J. Breitwisch, O. Bula, Jeff S. Brown, Bryant C. Colwill, Peter E. Cottrell, William T. Crocco Jr., Stephen S. Furkay, Michael J. Hauser, Terence B. Hook, Dennis Hoyniak, James M. Johnson, Chung Hon Lam, Rebecca D. Mih, J. Rivard, Atsushi Moriwaki, E. Phipps, Christopher S. Putnam, BethAnn Rainey, James J. Toomey, Mohammad Imran Younus   +21 more
openaire   +1 more source

GHz Asynchronous SRAM in 65nm

2009 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
This paper details the design of ≫ 1GHz pipelined asynchronous SRAMs in TSMC's 65nm GP process. We show how targeted timing assumptions improve an otherwise quasi delay-insensitive (QDI) design. The speed, area, and power of our SRAMs are compared to commercially available synchronous SRAMs in the same technology.
Jonathan Dama, Andrew Lines
openaire   +1 more source