Results 181 to 190 of about 13,836 (232)
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2016 8th International Symposium on Telecommunications (IST), 2016
Exploring possible vulnerabilities for making hardware Trojans helps designers to improve the security and trust of integrated circuits (ICs). This paper discusses the hardware Trojan possibility in SRAM to evaluate the security of SRAM and evaluates the effectiveness of existing detection methods.
Roghayeh Saeidi +1 more
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Exploring possible vulnerabilities for making hardware Trojans helps designers to improve the security and trust of integrated circuits (ICs). This paper discusses the hardware Trojan possibility in SRAM to evaluate the security of SRAM and evaluates the effectiveness of existing detection methods.
Roghayeh Saeidi +1 more
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Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium, 2002
SRAM designers and product engineers must balance the diverse aspects involved in developing and manufacturing quality ICs. This paper describes how cost and complexity design techniques to improve burn-in, noting implications for performance, power and density. >
William R. Reohr +4 more
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SRAM designers and product engineers must balance the diverse aspects involved in developing and manufacturing quality ICs. This paper describes how cost and complexity design techniques to improve burn-in, noting implications for performance, power and density. >
William R. Reohr +4 more
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SRAM CP: A Charge Recycling Design Schema for SRAM
2006An adiabatic charge-pump based charge recycling design was proposed in [1]. It was shown to save upto 15% energy on several DSP systems with no performance loss. In this paper, we illustrate new charge source multiplexing techniques that are especially targeted towards SRAM arrays.
Ka-Ming Keung, Akhilesh Tyagi
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Yield estimation of SRAM circuits using "Virtual SRAM Fab"
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009Static Random Access Memories (SRAMs) are key components of modern VLSI designs and a major bottleneck to technology scaling as they use the smallest size devices with high sensitivity to manufacturing details. Analysis performed at the "schematic" level can be deceiving as it ignores the interdependence between the implementation layout and the ...
Aditya Bansal +11 more
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Low voltage SRAMs and the scalability of the 9T Supply Feedback SRAM
2011 IEEE International SOC Conference, 2011Recent research has shown that minimum energy operation of digital circuits is in the sub-threshold region, and a good trade-off between power and performance can be achieved through operation at near threshold supply voltages. However, due to process variations and device mismatch at nanoscale technology nodes, voltage scaling of standard SRAMs is ...
Janna Mezhibovsky +2 more
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Electronics Letters, 2010 The design of a 6T SRAM cell with 20 nm junctionless (JL) MOSFETs is reported. It is shown that a 6T SRAM cell designed with JL MOSFETs achieves a high static noise margin (SNM) of 185 mV, retention noise or hold margin (RNM) of 381 mV and writability ...
A Kranti +2 more
exaly +2 more sources
Proceedings of the 2019 Great Lakes Symposium on VLSI, 2019
We present an in-memory computing SRAM macro for binary neural networks. The memory macro computes XNOR-and-accumulate for binary/ternary deep convolutional neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay-product than digital ASIC and achieves high accuracy in machine learning ...
Zhewei Jiang +3 more
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We present an in-memory computing SRAM macro for binary neural networks. The memory macro computes XNOR-and-accumulate for binary/ternary deep convolutional neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay-product than digital ASIC and achieves high accuracy in machine learning ...
Zhewei Jiang +3 more
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10th IEEE International NEWCAS Conference, 2012
A Neuro-SRAM design methodology composed of a set of basic SRAM cells is proposed, facilitating the identification of both the limiting mechanisms and the corrective design enhancements. Also, a neural decoder, which is the responsible for selecting these cells, is proposed and simulated.
Nayif Saleh +3 more
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A Neuro-SRAM design methodology composed of a set of basic SRAM cells is proposed, facilitating the identification of both the limiting mechanisms and the corrective design enhancements. Also, a neural decoder, which is the responsible for selecting these cells, is proposed and simulated.
Nayif Saleh +3 more
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Advanced test methods for SRAMs
2012 IEEE 30th VLSI Test Symposium (VTS), 2010Memory design and test represent very important issues. Memories are designed to exploit the technology limits to reach the highest storage density and high-speed access. The main consequence is that memory devices are statistically more likely to be affected by manufacturing defects.
Bosio, Alberto +4 more
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IEEE Design & Test of Computers, 2007
As FPGAs have grown larger and more complex, the value of the IP implemented in them has grown commensurately. Since SRAM FPGAs reload their programming data every time they are powered up, an adversary can potentially copy the program as it is being loaded.
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As FPGAs have grown larger and more complex, the value of the IP implemented in them has grown commensurately. Since SRAM FPGAs reload their programming data every time they are powered up, an adversary can potentially copy the program as it is being loaded.
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