Results 201 to 210 of about 13,836 (232)

SRAM Vmax stability considerations

2015 IEEE International Reliability Physics Symposium, 2015
The voltage overdrive of SRAM cells is shown to be of concern as the stability at Vmax can be worse than at Vmin. The Vmax stability is especially sensitive to high resistances on single devices in the bitcell. Highlighted in this paper are SRAM Vmax stability issues observed in a 28nm technology as well as the increased susceptibility of FinFET SRAM ...
David Burnett, Sriram Balasubramanian, Vivek Joshi, Sanjay Parihar, Jack M. Higman, C. Weintraub   +5 more
openaire   +1 more source

Ultralow-power SRAM technology

IBM Journal of Research and Development, 2003
An ultralow-standby-power technology has been developed in both 0.18-µm and 0.13-µm lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage six-transistor (6T) SRAM cell sizes are 4.81 µm2 and 2.34 µm2, corresponding respectively to the 0.18-µm and 0.13-µm design dimensions.
Randy W. Mann, W. W. (Bill) Abadeer, Matthew J. Breitwisch, O. Bula, Jeff S. Brown, Bryant C. Colwill, Peter E. Cottrell, William T. Crocco Jr., Stephen S. Furkay, Michael J. Hauser, Terence B. Hook, Dennis Hoyniak, James M. Johnson, Chung Hon Lam, Rebecca D. Mih, J. Rivard, Atsushi Moriwaki, E. Phipps, Christopher S. Putnam, BethAnn Rainey, James J. Toomey, Mohammad Imran Younus   +21 more
openaire   +1 more source

The Littlest SRAM

IEEE Spectrum, 2010
A new type of lithography that uses an electron beam to spark a chemical reaction could provide a way to build incredibly tiny transistors, which the chipmaking industry will require in a few years. Researchers from Taiwan and the University of California, Berkeley, say they've made static RAM that anticipates 16-nanometer chip features using a new ...
openaire   +1 more source

Enhancing Retention Voltage for SRAM

2017
In modern integrated chips, most of the power consumption comes from the memory blocks. These memory blocks require high rail voltages due to limited noise margins. Hence, the aim of this work is to design an assist circuitry which allows reduction in the retention voltage and consequently reduces the power consumption of memory.
Ankit Rehani, Sujay Deb, Suprateek Shukla   +2 more
openaire   +1 more source

Sram

2022
Vishal Sharma, Shivani Godha
openaire   +1 more source

SRAM

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007
Kevin Zhang 0001, Hiroyuki Yamauchi
openaire   +1 more source

Performance Analysis of Conventional SRAM with Higher Order SRAM Topologies

2018
The growth in digital consumer electronics has evoked a tremendous rise in performance of portable devices. To meet these demands, there is a need of primary memory and thus Static Random Access Memory (SRAM) serves this purpose. Technical innovations have provided the improved memory density and speed. Innovations in memory technology are reflected in
Ravneet Kaur, Garima Joshi, Maninder Kaur Saggu, Vishal Sharma   +3 more
openaire   +1 more source

Design of high stability, low power and high speed 12 T SRAM cell in 32-nm CNTFET technology

AEU - International Journal of Electronics and Communications, 2022
M Elangovan, Erfan Abbasian, Muthukumaran Gunasegeran   +2 more
exaly  

SRAM

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008
Hiroyuki Yamauchi, Peter Rickert
openaire   +1 more source

The Complementary FET (CFET) 6T-SRAM

IEEE Transactions on Electron Devices, 2021
Mohit Gupta, Pieter Weckx, Pieter Schuddinck   +2 more
exaly