Results 161 to 170 of about 55,876 (211)
Some of the next articles are maybe not open access.
Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium, 2002
SRAM designers and product engineers must balance the diverse aspects involved in developing and manufacturing quality ICs. This paper describes how cost and complexity design techniques to improve burn-in, noting implications for performance, power and density. >
William R. Reohr +4 more
openaire +1 more source
SRAM designers and product engineers must balance the diverse aspects involved in developing and manufacturing quality ICs. This paper describes how cost and complexity design techniques to improve burn-in, noting implications for performance, power and density. >
William R. Reohr +4 more
openaire +1 more source
SRAM CP: A Charge Recycling Design Schema for SRAM
2006An adiabatic charge-pump based charge recycling design was proposed in [1]. It was shown to save upto 15% energy on several DSP systems with no performance loss. In this paper, we illustrate new charge source multiplexing techniques that are especially targeted towards SRAM arrays.
Ka-Ming Keung, Akhilesh Tyagi
openaire +1 more source
Yield estimation of SRAM circuits using "Virtual SRAM Fab"
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009Static Random Access Memories (SRAMs) are key components of modern VLSI designs and a major bottleneck to technology scaling as they use the smallest size devices with high sensitivity to manufacturing details. Analysis performed at the "schematic" level can be deceiving as it ignores the interdependence between the implementation layout and the ...
Aditya Bansal +11 more
openaire +1 more source
Low voltage SRAMs and the scalability of the 9T Supply Feedback SRAM
2011 IEEE International SOC Conference, 2011Recent research has shown that minimum energy operation of digital circuits is in the sub-threshold region, and a good trade-off between power and performance can be achieved through operation at near threshold supply voltages. However, due to process variations and device mismatch at nanoscale technology nodes, voltage scaling of standard SRAMs is ...
Janna Mezhibovsky +2 more
openaire +1 more source
10th IEEE International NEWCAS Conference, 2012
A Neuro-SRAM design methodology composed of a set of basic SRAM cells is proposed, facilitating the identification of both the limiting mechanisms and the corrective design enhancements. Also, a neural decoder, which is the responsible for selecting these cells, is proposed and simulated.
Nayif Saleh +3 more
openaire +1 more source
A Neuro-SRAM design methodology composed of a set of basic SRAM cells is proposed, facilitating the identification of both the limiting mechanisms and the corrective design enhancements. Also, a neural decoder, which is the responsible for selecting these cells, is proposed and simulated.
Nayif Saleh +3 more
openaire +1 more source
Proceedings of the 2019 Great Lakes Symposium on VLSI, 2019
We present an in-memory computing SRAM macro for binary neural networks. The memory macro computes XNOR-and-accumulate for binary/ternary deep convolutional neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay-product than digital ASIC and achieves high accuracy in machine learning ...
Zhewei Jiang +3 more
openaire +1 more source
We present an in-memory computing SRAM macro for binary neural networks. The memory macro computes XNOR-and-accumulate for binary/ternary deep convolutional neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay-product than digital ASIC and achieves high accuracy in machine learning ...
Zhewei Jiang +3 more
openaire +1 more source
IEEE Design & Test of Computers, 2007
As FPGAs have grown larger and more complex, the value of the IP implemented in them has grown commensurately. Since SRAM FPGAs reload their programming data every time they are powered up, an adversary can potentially copy the program as it is being loaded.
openaire +1 more source
As FPGAs have grown larger and more complex, the value of the IP implemented in them has grown commensurately. Since SRAM FPGAs reload their programming data every time they are powered up, an adversary can potentially copy the program as it is being loaded.
openaire +1 more source
Advanced test methods for SRAMs
2012 IEEE 30th VLSI Test Symposium (VTS), 2010Memory design and test represent very important issues. Memories are designed to exploit the technology limits to reach the highest storage density and high-speed access. The main consequence is that memory devices are statistically more likely to be affected by manufacturing defects.
Bosio, Alberto +4 more
openaire +1 more source
Debiasing of SRAM PUFs: Selection and Balancing
2019 IEEE International Workshop on Information Forensics and Security (WIFS), 2019Fuzzy commitment is used to bind a secret key to an SRAM-PUF observation vector. The fuzzy commitment scheme is secure as long as the observation vector has full entropy. Here, we assume that the observation vectors are biased, and explore two elementary schemes for debiasing: Selection and balancing.
Kusters, Lieneke, Willems, Frans M.J.
openaire +2 more sources
IBM Journal of Research and Development, 2007
The IBM POWER6™ microprocessor presented new challenges to array design because of its high-frequency requirement and its use of 65-nm silicon-on-insulator (SOI) technology. Advancements in performance (2X to 3X improvement over the 90-nm generation) and design margins (cell stability, writability, and redundancy coverage) were major focus areas.
Donald W. Plass, Yuen H. Chan
openaire +1 more source
The IBM POWER6™ microprocessor presented new challenges to array design because of its high-frequency requirement and its use of 65-nm silicon-on-insulator (SOI) technology. Advancements in performance (2X to 3X improvement over the 90-nm generation) and design margins (cell stability, writability, and redundancy coverage) were major focus areas.
Donald W. Plass, Yuen H. Chan
openaire +1 more source