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Yield-Aware Leakage Power Reduction of On-Chip SRAMs

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SRAM-Based Unique Chip Identifier Techniques

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016
Integrated circuit (IC) identification using unclonable digital fingerprints facilitates the authentication of ICs, device tracking, and cryptographic functions. In this paper, we present two hardware methods exploiting the inherent process-induced mismatch of SRAM cells.
Srivatsan Chellappa, Lawrence T. Clark
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A chip-stacked memory for on-chip SRAM-rich SoCs and processors

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009
Advanced SoC chips used in multimedia devices such as mobile phones have a number of dedicated functional IP cores, including 3D graphics and video codec, and require local memories with high bit density. Each IP core is connected to closely positioned local memories for fast access and wide bandwidth. The simultaneous operation of all of IP cores on a
Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno   +8 more
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An on-chip test scheme for SRAMs

Proceedings of IEEE International Workshop on Memory Technology, Design, and Test, 2002
Semiconductor technology continues to progress dramatically. With the increasing density, the testing of RAM chips has become progressively more difficult. In this paper, a new approach to simplify the testing of large SRAMs (static RAMs), embedded in VLSI chips or as stand-alone chips, by incorporating additional circuitry is proposed. >
P.K. Lala, A. Walker
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Experimental fault analysis of 1 Mb SRAM chips

Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125), 2002
Analyzing 1,000 faulty 1 Mb SRAM chips that were randomly selected from a single manufacture, we found 251 stuck-at cell faults, 5 stuck-at bit-line faults, 1 stuck-at word-line fault, 46 neighborhood-pattern-sensitive faults, and other kinds of faults. Under the condition that I/sub dd/=4.5 I; temperature=70/spl deg/C, and load capacity C/sub L/=30 pF,
H. Goto, S. Nakamura, K. Iwasaki
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Design and test of an SRAM chip

2013 IEEE 10th International Conference on ASIC, 2013
A fully customized 8×8 bits SRAM chip, based on Chartered 0.35 um EEPROM CMOS technology, is designed and taped-out for low-power and low-cost electronic equipment. According to test results, when the supply voltage is 3.3 V and clock frequency is 20 MHz, the chip can work correctly, and the performance reaches the design specifications, the access ...
null Wenbin Liu, null Jinhui Wang, null Ligang Hou, null Hongyan Yang, null Jianbo Kang   +4 more
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BIST method of SRAM for network-on-chip

2015 12th IEEE International Conference on Electronic Measurement & Instruments (ICEMI), 2015
Network-on-chip (NoC) is becoming promising communication architecture for the next-generation system on chips. Intellectual property (IP) core is an important part of NoC system, this paper puts SRAM as an IP core to complete the test study of SRAM. We present a Built-in self-test (BIST) method for SRAM of network-on-chip based on reusing network-on ...
null Xu Chuanpei, null Tao Yi, null Wan Chunting   +2 more
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On-Chip VDC Circuit for SRAM Power Management

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2007
Leakage current becomes the dominant factor for contributing to the static power consumption. Power management technique is then required to bring down the power consumption. One of the most effective methods is to reduce the power supply voltage in the standby mode or in the power down active mode.
C.F. Lee, Wesley Lin, F.S. Lai, S.C. Lin
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Chip-on-chip technology with copper through-plug for 0.15 μm SRAM

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695), 2004
SRAM reliability impact and MOSFET electrical characteristics with copper (Cu) through-plug for three-dimensional (3-D) integration are examined and some degradation modes are inspected. Although the initial chip yield of chip-on-chip (COC) sample is comparable to references, the degradation occurs after high-temperature-storage (HTS) test.
M. Matsuo, K. Kasai, Y. Okayama, K. Ishimaru, N. Matsunaga, H. Yamaguchi, N. Otsuka, N. Hayasaka   +7 more
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Unclonable key Generator Based on Chip signature and SRAM-PUF of ATmega328P chip

2018 28th International Conference on Computer Theory and Applications (ICCTA), 2018
Embedded devices are now taking over the world, their presence in everyone's pocket and home arouses questions around privacy and security concerns. What amplifies these concerns are the rapid spread of internet of things (IOT) devices and smart meters across the world.
Amr Elmestekawi, Ashraf Tammam, Hanady Issa   +2 more
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