Results 151 to 160 of about 10,430 (199)

Challenging on-chip SRAM security with boot-state statistics

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2017
On-chip memory is regarded by most secure system designers as a safe memory space, beyond the eyes of all but the most sophisticated attackers. Once a value is overwritten or the power has been removed, it is assumed that the data stored inside fully ceases to persist.
Joseph McMahan, Weilong Cui, Liang Xia, Jeff Heckey, Frederic T. Chong, Timothy Sherwood   +5 more
openaire   +1 more source

Self-Repairing SRAM Using On-Chip Detection and Compensation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010
In nanometer scale static-RAM (SRAM) arrays, systematic inter-die and random within-die variations in process parameters can cause significant parametric failures, severely degrading parametric yield. In this paper, we investigate the interaction between the inter-die and intra-die V t variations on SRAM read and write failures.
Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy   +4 more
openaire   +1 more source

Ultralow Power System-on-Chip SRAM Characterization by Alpha and Neutron Irradiation

IEEE Transactions on Nuclear Science, 2021
The static random access memory (SRAM) of an ultralow power system-on-chip (SoC) was tested for single-event upsets (SEUs) using alpha particles and neutron beam sources. The measurements are compared to those of an SRAM-based field-programmable gate array (FPGA), built on a similar technology node. The results reveal opposite trends in the two devices
Avner Haran, Nir M. Yitzhak, Eran Mazal-Tov, Eitan Keren, David David, Nati Refaeli, Enrico Preziosi, Roberto Senesi, Carlo Cazzaniga, Christopher D. Frost, Tzach Hadas, Uzi Zangi, Carla Andreani   +12 more
openaire   +3 more sources

A 5V-only single chip microcomputer with nonvolatile SRAM

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1984
An 8b single chip microprocessor with a memory containing 32Kb of ROM, 512b of RAM and 512b of nonvolatile SRAM, implemented in 4μm double poly floating gate technology, will be described.
P. Rosini, R. Finaurini, M. Gaibotti
openaire   +1 more source

A 256K SRAM with on-chip power supply conversion

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1987
A 47.2mm2SRAM utilizing an on-chip power supply conversion and allowing full synchronous operation at either 5.0V or 3.3V pin voltage without performance penalty will be discussed. The chip with a six-device cell size of 109μm2has been built in a 0.7μm CMOS DRAM technology with silicides and double level metal.
A. Roberts, J. Dreibelbis, G. Braceras, J. Gabric, L. Gilbert, R. Goodwin, E. Hedberg, T. Maffitt, L. Meuniar, D. Moran, null Phuong Nguyen, D. Reed, D. Reismiller, R. Sasaki   +13 more
openaire   +1 more source

A scheme for multiple on-chip signature checking for embedded SRAMs

Proceedings European Design and Test Conference. ED & TC 97, 2000
Embedded read/write memories are integral parts of many VLSI chips designed for specific applications in the areas of computer communications, multimedia, and digital signal processing. Testing an embedded memory poses a challenge to a system test engineer, due to its limited controllability and observability.
M.F. Abdulla, C.P. Ravikumar, Anshul Kumar   +2 more
openaire   +1 more source

On-Chip Delay Measurement Circuit for Reliability Characterization of SRAM

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016
This paper represents a framework for on-chip delay measurement, which will be helpful in measuring the impact of device level variability on memory access time. Commercial frameworks for simulating circuit degradation due to device aging effects are not available.
Pankaj Verma, Rohit Halba, Hemant Patel, Maryam Shojaei Baghini   +3 more
openaire   +1 more source

Experimental Evaluation of Transient Effects on SRAM-based FPGA Chips

2005 International Conference on Microelectronics, 2006
This paper presents an experimental evaluation of transient effects on SRAM-based FPGAs. A total of 9000 transient faults were injected into the target FPGA using Power Supply Disturbances (PSD). The results show that nearly 60 percent of faults cause system failures and about 58 percent of the faults lead to corruption of the configuration data of the
A. Bakhoda, S.G. Miremadi, H.R. Zarandi
openaire   +1 more source

Immunity Evaluation of SRAM Chips for SOI and SI Technology

2019 12th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo), 2019
This paper mainly studies the electromagnetic immunity of two kinds of static random access memory (SRAM) chips using bulk silicon (SI) and insulator silicon (SOI) technologies respectively, and the effect of temperature on chip immunity. Direct power injection (DPI) method was used to test the immunity of each functional pin of the two chips, and the ...
Xujing Wu, Mengjun Wang, Jianfei Wu, Hong Li, Binhong Li, Ning Hao, Jiantou Gao, Hongli Zhang   +7 more
openaire   +1 more source

An on-chip circuit for timing measurement of SRAM IP

2017 IEEE 12th International Conference on ASIC (ASICON), 2017
The timing of silicon IPs should be measured before they are integrated into chips. Embedded solutions are needed for timing measurement of silicon IPs. This paper introduces a circuit design for timing measurement of SRAM IP. A new circuit is designed for the measurement of setup time, hold time and access time.
Xianjie Long, Qin Wang, Jianfei Jiang, Nin Guan   +3 more
openaire   +1 more source