Results 41 to 50 of about 10,430 (199)

Emerging Memory and Device Technologies for Hardware‐Accelerated Model Training and Inference

Advanced Electronic Materials, EarlyView.
This review investigates the suitability of various emerging memory technologies as compute‐in‐memory hardware for artificial intelligence (AI) applications. Distinct requirements for training‐ and inference‐centric computing are discussed, spanning device physics, materials, and system integration.
Yoonho Cho, Dae‐won Kim, Yujin Kim, Jung‐Heum Na, Yuwon Jeong, Dong‐Yeop Lee, Shinhyun Choi   +6 more
wiley   +1 more source

Single ended 12T cntfet sram cell with high stability for low power smart device applications

e-Prime: Advances in Electrical Engineering, Electronics and Energy
Static random-access memory (SRAM) is the most prevalent type of memory used in current system-on-chips (SOC). SRAMs built using Complementary metal oxide semiconductor (CMOS) transistors, suffer from low stability and significant power dissipation at ...
S. Jayanthi, P. Raja, M. Elangovan, T.S. Murugesh   +3 more
doaj   +1 more source

On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing [PDF]

, 2008
In this paper, a chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented. The chip is a first experimental prototype of reduced size to validate the implemented circuits and system level techniques ...
Acosta Jiménez, Antonio José, Civit Balcells, Antón, Jiménez Moreno, Gabriel, Linares Barranco, Alejandro, Linares Barranco, Bernabé, Pérez Carrasco, José Antonio, Serrano Gotarredona, Clara, Serrano Gotarredona, María Teresa, Serrano Gotarredona, Rafael   +8 more
core  

Carbon Nanotube Based Delay Model For High Speed Energy Efficient on Chip Data Transmission Using: Current Mode Technique

, 2014
Speed is a major concern for high density VLSI networks. In this paper the closed form delay model for current mode signalling in VLSI interconnects has been proposed with resistive load termination. RLC interconnect line is modelled using characteristic
Chandel, Rajeevan, Jadav, Sunil, Vashistah, Munish   +2 more
core   +1 more source

Single-Chip Motes and SRAM PUF: Feasibility Study

2024 IEEE Workshop on Crystal-Free/-Less Radio and System-Based Research for IoT (CrystalFreeIoT)
Physically unclonable functions (PUFs) are used as low-cost cryptographic primitives that extract key material from manufacturing variabilities of a device. All microcontrollers have on-chip SRAM; the power-up state of SRAM cells provides one way of obtaining a random output. However, not every SRAM can be used as a PUF.
Faour, Sara, Korecic, Blaz, Vučinić, Mališa, Maksimovic, Filip, Burnett, David, Mühlethaler, Paul, Watteyne, Thomas   +6 more
openaire   +3 more sources

Three-dimensional SRAM design with on-chip access time measurement

Electronics Letters, 2011
An SRAM design in a 3D 0.18 µm silicon-on-insulator technology is presented. A novel delay-locked loop based access time measurement circuit was designed on-chip for accurately evaluating the 3D SRAM performance. Results show that a 32% improvement in the access time is gained by using 3D technology.
X. Chen, T. Zhu, W.R. Davis
openaire   +1 more source

Flexible Memory: Progress, Challenges, and Opportunities

Advanced Intelligent Discovery, EarlyView.
Flexible memory technology is crucial for flexible electronics integration. This review covers its historical evolution, evaluates rigid systems, proposes a flexible memory framework based on multiple mechanisms, stresses material design's role, presents a coupling model for performance optimization, and points out future directions.
Ruizhi Yuan, Sen Chen, Minghui Guo, Ziliang Cui, Yujie Du, Jing Liu   +5 more
wiley   +1 more source

A novel system architecture for real-time low-level vision [PDF]

, 1999
A novel system architecture that exploits the spatial locality in memory access that is found in most low-level vision algorithms is presented. A real-time feature selection system is used to exemplify the underlying ideas, and an implementation based on
Benedetti, A., Perona, P.
core  

Toward Capacitive In‐Memory‐Computing: A Device to Systems Level Perspective on the Future of Artificial Intelligence Hardware

Advanced Intelligent Discovery, EarlyView.
Capacitive, charge‐domain compute‐in‐memory (CIM) stores weights as capacitance,eliminating DC sneak paths and IR‐drop, yielding near‐zero standbypower. In this perspective, we present a device to systems level performance analysis of most promising architectures and predict apathway for upscaling capacitive CIM for sustainable edge computing ...
Kapil Bhardwaj, Ella Paasio, Sayani Majumdar   +2 more
wiley   +1 more source

A programmable microsystem using system-on-chip for real-time biotelemetry [PDF]

, 2005
A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument ...
Cooper, J.M., Cui, L., Cumming, D.R.S., Hammond, P.A., Johannessen, E.A., Reid, S.W.J., Wang, L.   +6 more
core   +1 more source