Results 71 to 80 of about 10,430 (199)
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
Near-sensor data analytics is a promising direction for IoT endpoints, as it minimizes energy spent on communication and reduces network load - but it also poses security concerns, as valuable data is stored or sent over the network at various stages of ...
Benini, Luca +11 more
core +1 more source
ABSTRACT Cyclic executives (CEs) offer the advantage of ensuring complete determinism with minimal runtime overhead, often making them the preferred choice for safety‐critical real‐time systems. However, generating CEs for multicore processors while addressing task precedence and exclusion relations presents significant challenges.
Bruno Nogueira +4 more
wiley +1 more source
EMERGING ARCHITECTURES FOR PROCESSOR-IN-MEMORY CHIPS: TAXONOMY AND IMPLEMENTATION
The emergence of PIM (processing-in-memory) die and Date-Centric systems (DCS) and near- data processing approach (NDP) has given rise to the need of developing architectural taxonomy for multi-core PNM (processing near memory) hardware with multi-level ...
A Lapshinsky Valery
doaj
Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism
Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher ...
Roman Golman +2 more
doaj +1 more source
Ultrathin Hafnium‐Based Ferroelectric Devices for In‐Memory Computing Applications
Hafnium‐based ferroelectric devices exhibit advantages in nonvolatile storage, low power consumption, and ultrahigh operation speed, positioning them as strong candidates for constructing hardware neural networks. ABSTRACT The discovery of ferroelectricity in HfO2‐based ferroelectrics at the ultrathin scale has reignited enthusiasm for ferroelectric ...
Chenghong Mo +3 more
wiley +1 more source
With the rapid development of various technologies, processing large amounts of data has become essential. To address this trend, various high-density and high-performance memories have emerged.
Ho-Sung Lee +4 more
doaj +1 more source
ABSTRACT This paper presents the development and validation of a scalable platooning system based on the predecessor‐following (PF) topology, designed for low‐cost follower platforms. It integrates key technologies such as localization, path planning, profile generation, and low‐level control to create a practical solution.
Dongwoo Seo, Jinhee Lee, Jaeyoung Kang
wiley +1 more source
Design and qualification of the SEU/TD Radiation Monitor chip [PDF]
This report describes the design, fabrication, and testing of the Single-Event Upset/Total Dose (SEU/TD) Radiation Monitor chip. The Radiation Monitor is scheduled to fly on the Mid-Course Space Experiment Satellite (MSX).
Blaes, Brent R. +4 more
core +1 more source
Complementary Logic Driven by Dielectrophoretic Assembly of 2D Semiconductors
Scalable, parallel fabrication of complementary logic gates is demonstrated using electric‐field‐driven deterministic assembly of electrochemically exfoliated 2D n‐type MoS2 and p‐type WSe2 nanosheets. This strategy yields MoS2 and WSe2 transistors featuring average mobilities of 4.3 and 3.0 cm2 V−1 s−1, respectively, and on/off ratios of > 104 ...
Dongjoon Rhee +10 more
wiley +1 more source
Hydra: An Accelerator for Real-Time Edge-Aware Permeability Filtering in 65nm CMOS
Many modern video processing pipelines rely on edge-aware (EA) filtering methods. However, recent high-quality methods are challenging to run in real-time on embedded hardware due to their computational load. To this end, we propose an area-efficient and
Benini, Luca +6 more
core +1 more source

