Results 191 to 200 of about 2,464,424 (247)

Static and Dynamic Noise Margins of Logic Circuits

IEEE Journal of Solid-State Circuits, 1979
Explaining four basic types of noise, and by showing the various methods, together with boundary conditions, which can be used to find the worst case noise margins. A flip-flop setup is advised which can be used for measurements and computer simulations, both for static and dynamic noise margins.
J Lohstroh
exaly   +2 more sources

Enhancing Static Noise Margin While Reducing Power Consumption

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), 2013
The unrelenting scaling of CMOS devices has brought their dimensions down to few tens of nanometers. In such sizes, the reliability margins drop ominously and the leakage power dissipation increases significantly. This paper presents a non-conventional transistor-sizing method for improving reliability by increasing the static noise margin, while ...
Azam Beg
exaly   +3 more sources

Static Noise Margin of 6T SRAM Cell in 90-Nm CMOS

2011 UkSim 13th International Conference on Computer Modelling and Simulation, 2011
This paper examines the factors that affect the Static Noise Margin (SNM) of a 6T Static Random Access Memory (SRAM) cell designed in 90-nm CMOS. In this paper, the SRAM cell is simulated and noise margins are obtained while varying several parameters that affect SRAM operations. These parameters are temperature, threshold voltage, supply voltage, cell
Christiensen D. C. Arandilla, Anastacia B. Alvarez, Christian Raymund K. Roque   +2 more
exaly   +2 more sources

Static Noise Margin Analysis of Various SRAM Array

2020 International Conference on Communication and Signal Processing (ICCSP), 2020
Decreasing the power consumption and growing the noise margin have turn out to be two imperative topics in the artwork SRAM design. Recent works have proven that the traditional 6T SRAM suffer stability degradation, as a consequence,8T and 10T designs had been implemented to enhancing the cellular stability.
Anjana R Krishnan, G Shekar
exaly   +2 more sources

Analyzing Static Noise Margin for Sub-Threshold SRAM in 65nm CMOS

Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005., 2005
This paper evaluates the static noise margin (SNM) of 6T SRAM bitcells operating in sub-threshold. We analyze the dependence of SNM during both hold and read modes on supply voltage, temperature, transistor sizes, local transistor mismatch due to random doping variation, and global process variation in a commercial 65nm technology.
Benton H. Calhoun, Anantha P. Chandrakasan   +1 more
exaly   +2 more sources

Static Noise Margin Variation for Sub-Threshold SRAM in 65-Nm CMOS

IEEE Journal of Solid-State Circuits, 2006
The increased importance of lowering power in memory design has produced a trend of operating memories at lower supply voltages. Recent explorations into sub-threshold operation for logic show that minimum energy operation is possible in this region. These two trends suggest a meeting point for energy-constrained applications in which SRAM operates at ...
A P Chandrakasan
exaly   +3 more sources

Static Noise Margin Analysis of 6T SRAM

2020 IEEE International Conference for Innovation in Technology (INOCON), 2020
The complementary metal oxide semiconductor (CMOS) technology has long benefitted from the conventional scaling trends which require reducing the critical dimensions of the transistor. The static random access memory (SRAM) has also benefitted from such downsizing and has long been used as cache memory. In this paper, we present the static noise margin
Vijay Singh, Sanjay Kumar Singh, Raman Kapoor   +2 more
openaire   +1 more source

Statistical analysis of static noise margins

2015 European Conference on Circuit Theory and Design (ECCTD), 2015
This paper presents preliminary results of a statistical analysis of the SNM of inverters (as the basic element of any SRAM bit cell). Results are statistical meaningful as probabilities are calculated accurately, and should lead to more precise, faster, and better yield estimates. Comparisons with Monte Carlo simulations are supporting such claims.
Valeriu Beiu, Mihai Tache
openaire   +1 more source

Enabling sizing for enhancing the static noise margins

International Symposium on Quality Electronic Design (ISQED), 2013
This paper suggests a transistor sizing method for classical CMOS gates implemented in advanced technology nodes and operating at low voltages. The method relies on upsizing the length (L) of all transistors uniformly, and balancing the voltage transfer curves (VTCs) for maximizing the static noise margins (SNMs). We use the most well-known CMOS gates (
Valeriu Beiu, Azam Beg, Walid Ibrahim, Fekri Kharbash, Massimo Alioto   +4 more
openaire   +2 more sources

Static series-voltage noise margins of CBL, CSL and CMOS

9th International Conference on Electronics, Circuits and Systems, 2003
The concept of noise margin is very important in the design and application of digital logic circuits. Noise margin is the maximum spurious signal that can be accepted by the device when used in the system, whilst still operating correctly. In this work the static series-voltage noise margin of CBL (Current-Balanced Logic), CSL (Current-Steering Logic)
Butković, Željko, Szabo, Aleksandar
openaire   +2 more sources