Results 201 to 210 of about 2,464,424 (247)
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Static Noise Margin Analysis for Cryo-CMOS SRAM Cell
2021 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), 2021In this work, we analyzed the static noise margin (SNM) of cryo-CMOS SRAM cells operated at superthreshold (Vdd = 0.75 V) and subthreshold (Vdd = 0.2 V) regions. The impact of the temperature and write-assist (WA) technique on the ultra-thin-body (UTB) SOI SRAM cell has been examined.
Vita Pi-Ho Hu, Chang-Ju Liu
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International Journal of Circuit Theory and Applications, 2012
ABSTRACTThe cell static noise margin (SNM) is widely used as a stability criterion for static random‐access memory cells design. This parameter is typically determined through electrical simulations since direct experimental characterization of SNM is not achievable.In this work, we present a methodology that provides an indirect measurement of the SNM
José Luis Merino +3 more
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ABSTRACTThe cell static noise margin (SNM) is widely used as a stability criterion for static random‐access memory cells design. This parameter is typically determined through electrical simulations since direct experimental characterization of SNM is not achievable.In this work, we present a methodology that provides an indirect measurement of the SNM
José Luis Merino +3 more
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The Static Noise Margin of SRAM cells
ESSCIRC '86: Twelfth European Solid-State Circuits Conference, 1986A simulation method is presented which makes it possible to analyze the stability of SRAM cells in terms of Static Noise Margin (SNM). With this method the effect of supply voltage reduction below the conventional 5V on the stability of resistor load (R-load) and full CMOS (6T) SRAM cells is analyzed.
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Static-noise margin analysis of MOS SRAM cells
IEEE Journal of Solid-State Circuits, 1987The stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation. Explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived.
E. Seevinck, F.J. List, J. Lohstroh
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Statistical Simulation of Static Noise Margin Variability in Static Random Access Memory
IEEE Transactions on Semiconductor Manufacturing, 2010In this paper, we examine the impact of random-dopant-fluctuation (RDF), process-variation-effect (PVE), and workfunction-fluctuation (WKF), on 16-nm-gate metal-oxide-semiconductor field-effect-transistor (MOSFET) static random access memory (SRAM) cells.
Yiming Li, Hui-Wen Cheng, Ming-Hung Han
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Estimation methods for static noise margins in CMOS subthreshold logic circuits
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017Operating CMOS circuits at subthreshold supply voltages is an attractive solution for substantial energy reduction, at the expense of strong timing performance degradation, for a broad range of battery operated appliances. One of the challenges of this approach in current technology nodes is the reduced available noise margin when operating at low ...
Felipe T. Bortolon +3 more
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Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration
IEICE Transactions on Electronics, 2008An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random Vth variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed.
Hirofumi Shinohara +2 more
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A compact and low-power SRAM with improved read static noise margin
2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008An efficient static random access memory (SRAM) is presented in this paper. By using a newly developed architecture based on ldquopreequalizerdquo scheme, the geometry ratio between the pull-up and pull-down driver transistors of conventional 6-T cell will be similar to that of familiar inverter, thereby making the SRAM be provided with an improved ...
Cihun-Siyong Alex Gong +4 more
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Static noise margin and power dissipation analysis of various SRAM topologies
2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), 2013In this paper we analyze and compare 8 different SRAM cell topologies that are suitable for low power embedded memory design in terms of power consumption, area, static noise margin (SNM) and read and write delays, which are the basic parameters affecting the performance of an SRAM cell. The circuit simulation and analysis were carried out using HSPICE
Prajna Mishra, Eugene John, Wei-Ming Lin
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Stability and Static Noise Margin Analysis of Low-Power SRAM
2008 IEEE Instrumentation and Measurement Technology Conference, 2008To overcome the read data destruction and to gain stability at Iow-VDD a seven-transistor (7T) SRAM cell is implemented and compared with the conventional six-transistor (6T) SRAM cell. To illustrate the robust performance of an 8-bit SRAM statistical simulation and data analysis by considering the process variations and mismatch was conducted for ...
Rajasekhar Keerthi, Chein-in Henry Chen
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