Results 211 to 220 of about 2,464,424 (247)

Static Noise Margin Analysis of 6T SRAM Cell

2016
This report describes the SNM calculation and analysis of SRAM cell which are obtained from simulations performed in Cadence Virtuoso 90 nm technology. The SRAM cell structure is implemented with a compact structure of six transistors. Static noise margin is found from the butterfly curve obtained for read, write, and hold modes of operation.
Abinkant A. Jose, Nikhitha C. Balan
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Supply voltage reduction in SRAMs: Impact on Static Noise Margins

2008 IEEE International Conference on Automation, Quality and Testing, Robotics, 2008
Reducing leakage in memories is critical to reduce static power consumption in nanometric technologies. A wide-spread technique for reducing the leakage consists of lowering the supply voltage on the SRAM module. The paper investigates the effect of lowering the supply voltage on the robustness of a 6T SRAM cell, both in saturation and sub-threshold ...
E. I. Vatajelu, J. Figueras
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Static noise margin analysis of double-gate MOSFETs SRAM

2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2009
A continuous, analytic model of double-gate MOSFETs is used to simulate all transistors in a six-transistor (6T) SRAM cell. The static noise margin (SNM) of 6T-SRAM cells is investigated as a function of supply voltage, threshold voltage, temperature effects, and the size of transistors.
null Qian Xie, null Mei Zhao, Jun Xu, Yuan Taur   +3 more
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Statistical Modeling of Read Static Noise Margin for 6-Transistor SRAM cell

2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019
This paper proposes a statistical approach to modeling the single-sided read static noise margin (RSNM) of a 6-transistor SRAM cell. The proposed modeling considers threshold voltage (Vth), channel length, and width variations. In addition, it considers Vth roll-off and drain-induced barrier-lowering effect of short channel transistors.
Byeong-Jun Bang, Hyun-jeong Kwon, Young Hwan Kim, Kyoung-Rok Cho, Hi-Seok Kim   +4 more
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Analytic modeling of static noise margin considering DIBL and body bias effects

2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017
In this paper an analytic model of the inverter static noise margin (SNM) is presented. The drain-induced barrier lowering (DIBL) effects are considered in view of the fact that their influence becomes more critical in nanometer (below 90 nm) bulk CMOS nodes, as devices are dimensioned with minimum sizes and operate in sub-threshold region.
Fabian Olivera, Antonio Petraglia
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One-Sided Static Noise Margin and Gaussian-Tail-Fitting Method for SRAM

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014
In this paper, we propose a method to estimate the read failure rate of a static random access memory (SRAM) cell. Conventional read stability metrics cannot accurately estimate the read failure probability as technology scales down, because some metrics cannot characterize read stability and others can no longer be approximated to a known distribution.
Hanwool Jeong, Younghwi Yang, Junha Lee, Jisu Kim, Seong-Ook Jung   +4 more
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Re-Examination of Impact of Intrinsic Dopant Fluctuations on Static RAM (SRAM) Static Noise Margin

Japanese Journal of Applied Physics, 2005
The impacts of intrinsic threshold voltage (V th) fluctuations in metal oxide semiconductor field effect transistors (MOSFETs) on the static random access memory (SRAM) static noise margin (SNM) are re-examined in the 90 nm to 45 nm technology generations on the basis of the 2003 International Technology Roadmap for Semiconductors
Fumihiko Tachibana, Toshiro Hiramoto
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Experimental characterization of the static noise margins of strained silicon complementary tunnel-FET SRAM

2017 47th European Solid-State Device Research Conference (ESSDERC), 2017
Half SRAM cells with strained Si nanowire complementary Tunnel-FETs (CTFET) have been fabricated to explore the capability of TFETs for 6T-SRAM. Static measurements on cells with outward faced n-TFET access transistors have been performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability.
Gia Vinh Luong, Sebastiano Strangio, Andreas T. Tiedemann, Patric Bernardy, Stefan Trellenkamp, Pierpaolo Palestri, Siegfried Mantl, Qing-Tai Zhao   +7 more
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Sensitivity of static noise margins to random doping variations in 6T SRAM cells

2007 International Semiconductor Device Research Symposium, 2007
SRAM bitcells are most negatively affected by random fluctuations of the doping concentration. The Static Noise Margins (SNM) of these circuits fluctuate from one cell to another because of random doping variations, mismatch, and inaccuracies during the fabrication process.
Liviu Oniciuc, Petru Andrei
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Static‐noise margin analysis for a scaled‐down CMOS memory cell

Electronics and Communications in Japan (Part II: Electronics), 1992
AbstractThe noise margins for CMOS SRAM cells composed of scaled‐down MOSFETs are described.First, an analytical method estimating the noise margins for the CMOS memory cells is proposed. Then scaled‐down MOSFET effects, i.e., the mobility degradation and the parasitic resistances will be considered.
Takakuni Douseki, Shin‐Ichiro Mutoh
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