Results 221 to 230 of about 2,464,424 (247)
Some of the next articles are maybe not open access.
SRAM Cell Static Noise Margin and VMIN Sensitivity to Transistor Degradation
2006 International Electron Devices Meeting, 2006The SRAM cell sensitivity to transistor degradation is understood using a novel test methodology. A new, semi-empirical model that captures the observed trends is derived. The key findings include (a) cell sensitivity to NBTI degradation is high when low NMOS VT/ high PMOS VT combination arises (b) NBTI contribution to product VMIN drift arises mainly ...
A. T. Krishnan +11 more
openaire +1 more source
Statistical (M-C) and static noise margin analysis of the SRAM cells
2013 Students Conference on Engineering and Systems (SCES), 2013For the first time through this paper, a Static Random Access Memory using 9T SRAM, 8T SRAM and 6T SRAM has been compared using N-curve and statistical analysis which demonstrated a multi-fold performance enhancement. In this paper, 9T SRAM cell with extra transistors compared to 8T SRAM and 6T SRAM cells, is giving the higher stability (SVNM, SINM ...
G. Prasad, R. Kusuma
openaire +1 more source
Temperature behavior of the voltage swings and the static noise margins of ISL and STL
IEEE Journal of Solid-State Circuits, 1982The voltage swing and the low-current-level static groundline voltage noise margins of integrated Schottky logic (ISL) Schottky transistor logic (STL) as a function of temperature and fan-out, are derived analytically for gates with and without an internal pull-up current.
J. Lohstroh, R.M. Pluta
openaire +1 more source
Static Series-Voltage Noise Margin for Schottky TTL
1998The concept of noise margin is very important in the design and application of digital logic circuits. Noise margin is the maximum spurious signal that can be accepted by the device when used in a system, whilst still operating correctly. In this work the methods of determining the static series-voltage noise margin and the obtained results for various
Szabo, Aleksandar, Butković, Željko
openaire +1 more source
Device Engineering to Improve SRAM Static Noise Margin
Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials, 2010J. Luo +5 more
openaire +1 more source
Regression Analysis of Static Noise Margin and Transconductance for Underlap Lengths of FinFET
2022 45th International Spring Seminar on Electronics Technology (ISSE), 2022Rituraj S. Rathore +1 more
openaire +1 more source
A Read-Static-Noise-Margin-Free SRAM Cell for Low-VDD and High-Speed Applications
IEEE Journal of Solid-State Circuits, 2006Y Nakazawa
exaly
Adaptive Static and Dynamic Noise Margin Improvement in Minimum-Sized 6T-SRAM Cells
Microelectronics Reliability, 2014Gabriel Torrens Caldentey +2 more
exaly
Calculation Method to Obtain Worst-Case Static Noise Margins of Logic Circuits
Electronics Letters, 1980J Lohstroh
exaly