Results 81 to 90 of about 2,469,367 (147)

Low-power fast (LPF) SRAM cell for write/read operation

, 2011
Power consumption and Static noise margin (SNM) are most important parameters for memory design. The main source of power consumption in SRAM cell is due to large voltage swing on the bitlines during write operation.
Singh, Ajay Kumar, Ajay Kumar Singh, C. M. R. Prabhu, Prabhu, C. M. R.   +3 more
core   +1 more source

86th Annual Meeting of the Meteoritical Society (2024)

Meteoritics &Planetary Science, Volume 59, Issue S1, Page A1-A468, August 2024.
wiley   +1 more source

Vertical tunneling FET with Ge/Si doping-less heterojunction, a high-performance switch for digital applications. [PDF]

Sci Rep, 2023
Cherik IC, Mohammadi S, Maity SK.
europepmc   +1 more source

Design and Analysis of Three New SRAM Cells

Majlesi Journal of Electrical Engineering
Three new SRAM cells are proposed in this paper. Increasing area overhead is the major concern in SRAM design. One of the new structures is included four transistors instead of six transistors as it is used in conventional 6T-SRAM cell for very high ...
Amir Ebrahimi, Ehsan Kargaran, Abbas Golmakani   +2 more
doaj  

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell. [PDF]

Micromachines (Basel), 2023
Priya GL, Rawat N, Sanagavarapu A, Venkatesh M, Andrew Roobert A.   +4 more
europepmc   +1 more source

SRAM stability metric under transient noise

ventional way to analyze the robustness of an SRAM bit cell is to quantify its immunity to static noise. The static immunity to disturbances like process and mi smatch variations, bulk noises, supply rings variations, temperature changes is well ...
Figueras Pàmies, Joan, Gómez Pau, Álvaro, Vatajelu, Elena Ioana, Renovell, Michel   +3 more
core  

Energy-Efficient and Variability-Resilient 11T SRAM Design Using Data-Aware Read-Write Assist (DARWA) Technique for Low-Power Applications. [PDF]

Sensors (Basel), 2023
Thirugnanam S, Soong LW, Prabhu CM, Singh AK.   +3 more
europepmc   +1 more source

An Optimal Design Method for Even-Stage Ring Oscillators with a CMOS Latch [PDF]

This paper describes an analysis of oscillation conditions in CMOS ring oscillators composed of even-stage inverters. A design method optimizing the oscillator's operational margin based on this analysis is also described.
中村, 和之, Nakamura, Kazuyuki, Kohara, Yusuke, Asano, Masaharu, Koike, Hiroki, ナカムラ, カズユキ   +5 more
core   +1 more source

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits. [PDF]

Micromachines (Basel), 2023
Priya GL, Saran P, Padhy SK, Agarwal P, Andrew Roobert A, Julus LJ.   +5 more
europepmc   +1 more source

Simulasi Pengaruh Statik Marjin Pada Arah Memutar Trayektori Roket (Simulation Of Static Margin Effect To Directional Rocket Trajectory)

, 2018
Paper ini mempelajari hubungan antara static margin, directional stability dan strategi belok menggunakan bank-to-turn yang diaplikasikan pada roket kendali, dalam hal ini rudal.
Larasmoyo Nugroho, Setiadi
core