Results 71 to 80 of about 2,469,367 (147)
CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-valued Logic Circuits
, 2017 We propose the feasible and scalable ternary CMOS (T-CMOS) device platform for a fully CMOS-compatible physical synthesis of multi-valued logic (MVL) circuits.
Sunhae Shin +7 more
core +1 more source
High Read Stability and Low Leakage Cache Memory Cell
, 2007 - Data in conventional six transistor (6T) static random access memory (SRAM) cells are vulnerable to noise due to the direct access to the data storage nodes through the bit lines during a read operation. A new nine transistor (9T) SRAM cell is proposed
Liu, Zhiyu +3 more
core +1 more source
A Robust Low Power Static Random Access Memory Cell Design [PDF]
, 2018 Stability of a Static Random Access Memory (SRAM) cell is an important factor when considering an SRAM cell for any application. The Static Noise Margin (SNM) of a cell, which determines the stability, varies under different operating conditions.
Pusapati, A. V. Rama Raju
core +2 more sources
Low-power reliable SRAM cell for write/read operation
, 2015 Low power SRAM cell is a critical component in modern VLSI systems. The major portion of the power dissipation in the SRAM cell is due to large voltage swing on the bit lines during write operation.
Singh, Ajay Kumar +1 more
core +1 more source
Investigation of Single-Event Upset in Graphene Nano-Ribbon FET SRAM Cell. [PDF]
Micromachines (Basel), 2023 Adesina NO.
europepmc +1 more source
Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET. [PDF]
Nanomaterials (Basel), 2023 Li S, Wu Z.
europepmc +1 more source
Analysis of 6T SRAM Cell in Different Technologies
, 2017 Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital
Siba Kumar Panda, Subhashree Rath
core +1 more source
Performance Degradation in Static Random Access Memory of 10 nm Node FinFET Owing to Displacement Defects. [PDF]
Micromachines (Basel), 2023 Bang M, Ha J, Lee G, Suh M, Kim J.
europepmc +1 more source
A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors. [PDF]
Nat Commun, 2023 Lee C +5 more
europepmc +1 more source