Results 61 to 70 of about 2,469,367 (147)

Demonstration of standrad ternary inverter based on CMOS technology

, 2016
We demonstrate a standard ternary inverter (STI) by using gate-last CMOS process with novel I-V characteristics based on off-state mechanism. Though the controllable ????? and ?????
Sunhae Shin, Jeong, Jae Won, Kyung Rok Kim, Esan Jang, Jae Won Jeong, Shin, Sunhae, Kim, Kyung Rok, Jang, Esan   +7 more
core   +1 more source

Junctionless 6T SRAM cell [PDF]

, 2010
The design of a 6T SRAM cell with 20 nm junctionless (JL) MOSFETs is reported. It is shown that a 6T SRAM cell designed with JL MOSFETs achieves a high static noise margin (SNM) of 185 mV, retention noise or hold margin (RNM) of 381 mV and writability ...
C.-W. Lee, Kranti, A., Razavi, P., Yan, R., N. Akhavan, R. Yan, Yu, R., Ferain, I., Lee, C.-W., Colinge, J.-P., A. Kranti, G.A. Armstrong, I. Ferain, P. Razavi, R. Yu, J.-P. Colinge, Armstrong, G. A., Akhavan, N.   +17 more
core   +1 more source

SNM analysis of 11NM shorted-gate and low-power 6T FinFET SRAM topologies

, 2015
This item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID.Seven design metrics were studied and evaluated to ...
Vernor, Dusten
core   +1 more source

Design and circuit applications of PTnMOSFET devices from planar to gate-all-around structures

Discover Electronics
In this work, we propose a punch-through nMOSFET (PTnMOSFET) as a practical alternative to pMOSFETs by adjusting the source/drain doping concentrations. This PTnMOSFET design simplifies device fabrication by eliminating the need for sizing adjustments or
Jyi-Tsong Lin, Yuan-Yu Chuang
doaj   +1 more source

Modeling and Analysis of Noise Margin in SET Logic

, 2007
In this paper the static noise margin for SET (single electron transistor) logic is defined and compact models for the noise margin are developed by making use of the MIB (Mahapatra-Ionescu-Banerjee) model.
Mahapatra, Santanu, Sathe, Chaitanya
core  

ULP Variability-insensitive SRAM design in sub-32nm UTBB FDSOI CMOS [PDF]

, 2011
International audienceThis paper describes a design approach based on optimization of embedded SRAMs that takes advantage of an Ultra-Thin Body and Box (UTBB) Fully-Depleted (FD) SOI CMOS process.
Makosiej, Adam, Amara, Amara, Thomas, Olivier, Vladimirescu, Andrei   +3 more
core  

The effect of compact modelling strategy on SNM and Read Current variability in Modern SRAM

, 2011
It has been shown that sub 100nm SRAM is particularly sensitive to stochastic device variability. In this paper we consider two correlated figures of merit for SRAM, Static Noise Margin (SNM) and Read Current.
Asenov, Asen, Roy, Scott, G. Roy, C. Millar, Reid, David, Millar, Campbell, Kovac, Urban, P. Asenov, S. Roy, Asenov, Plamen, Roy, Gareth, Adamu-Lema, Fikru, D. Reid, F. Adamu-Lema, A. Asenov, U. Kovac   +15 more
core   +1 more source

Robust asymmetric 6T-SRAM cell for low-power operation in nano-CMOS technologies

, 2010
An asymmetric 6T-SRAM cell design is presented for reliable lowpower circuit operation under large variability. A low overhead write assist circuit is added to increase the write-noise-margin (WNM) and improve the write speed/power.
Cheng, B., Cumming, D.R.S., Azam, T., Roy, S., D.R.S. Cumming, T. Azam, B. Cheng, S. Roy   +7 more
core   +1 more source

A 0.5-V Six-Transistor Static Random Access Memory with Ferroelectric-Gate Field Effect Transistors

, 2010
A 0.5 V six-transistor static random access memory (6T-SRAM) with ferroelectric-gate field-effect-transistors (Fe-FETs) is proposed and experimentally demonstrated for the first time. During the read and the hold, the threshold voltage (V
Shuhei Tanakamaru, Teruyoshi Hatanaka, Mitsue Takahashi, Kousuke Miyaji, Shigeki Sakai, Ryoji Yajima, Ken Takeuchi   +6 more
core   +1 more source

Importance sampling Monte Carlo simulations for accurate estimation of SRAM yield [PDF]

, 2008
Variability is an important aspect of SRAM cell design. Failure probabilities of Pfail=10-10 have to be estimated through statistical simulations. Accurate statistical techniques such as Importance Sampling Monte Carlo simulations are essential to ...
Croon, J.A., Wittich, O., J.A. Croon, O. Wittich, T.S. Doorn, Di Bucchianico, A.; id_orcid, Maten, ter, E.J.W., A. Di Bucchianico, E.J.W. ter Maten, Doorn, T.S.   +9 more
core   +1 more source