Results 221 to 230 of about 52,126 (300)
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Single bit line accessed high‐performance ultra‐low voltage operating 7T static random access memory cell with improved read stability

International journal of circuit theory and applications, 2021
Static random access memory (SRAM) bit cell is a prominent element for portable devices. The popularity of sleek designs and demand for longer battery life has driven memory cell into nanometer domain.
B. Rawat, P. Mittal
semanticscholar   +1 more source

A 32 nm single-ended single-port 7T static random access memory for low power utilization

Semiconductor Science and Technology, 2021
In this paper, a seven-transistor static random access memory (SRAM) bit cell with a single bitline architecture is proposed. This cell is designed at 32 nm and is operational at 300 mV. The static noise margin for the read and hold modes is 90 mV, while
B. Rawat, P. Mittal
semanticscholar   +1 more source

Single-Event Response of 22-nm Fully Depleted Silicon-on-Insulator Static Random Access Memory

IEEE Transactions on Nuclear Science, 2021
We are presenting single-event effect testing results on a 22-nm fully depleted silicon-on-insulator test chip from GlobalFoundries. The 128-Mb static random access memory (SRAMs) were irradiated with heavy ions, and the results are compared to previous ...
M. Casey   +6 more
semanticscholar   +1 more source

Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design

International journal of circuit theory and applications, 2021
Graphene nanoribbon and transition metal dichalcogenide field‐effect transistors (GNRFETs and TMDFETs) have emerged as favorable candidates to replace conventional metal‐oxide‐semiconductor (MOS) transistor in future technologies.
Erfan Abbasian   +2 more
semanticscholar   +1 more source

High-speed GaAs static random-access memory

IEEE Transactions on Electron Devices, 1982
An 8-bit fully decoded RAM test circuit has been designed and fabricated using enhancement-mode GaAs-MESFET's with the LPFL circuit approach. Correct operation of the circuit has been observed for a supply voltage varying from 3.5 to 7 V. An access time of 0.6 ns was measured for a total power consumption of 85 mW under nominal operating conditions ...
G. Bert   +3 more
openaire   +1 more source

Design of a Stable Low Power 11-T Static Random Access Memory Cell

J. Circuits Syst. Comput., 2020
In this paper, a 11-T static random-access memory (SRAM) cell has been examined that shows a fair reduction in read power dissipation while upholding the stability and moderate performance.
Ashish Sachdeva, V. Tomar
semanticscholar   +1 more source

Design of Low Power Half Select Free 10T Static Random-Access Memory Cell

J. Circuits Syst. Comput., 2020
This paper presents a circuit-level technique of designing a low power and half select free 10T Static Random-Access Memory Cell (SRAM). The proposed cell works with single end read operation and differential write operation.
Ashish Sachdeva, V. Tomar
semanticscholar   +1 more source

Nano-optomechanical static random access memory (SRAM)

2015 28th IEEE International Conference on Micro Electro Mechanical Systems (MEMS), 2015
This paper reports an on chip nano-optomechanical SRAM, which is integrated with light modulation system on a single silicon chip. In particular, a doubly-clamped silicon beam shows bistability due to the non-linear optical gradient force generated from a ring resonator. The memory states are assigned with two stable deformation positions, which can be
B. Dong   +7 more
openaire   +1 more source

Design and statistical analysis of low power and high speed 10T static random access memory cell

International journal of circuit theory and applications, 2020
Static random access memory (SRAM)‐based cache memory is an essential part of electronic devices. As the technology node reduces, the power loss and stability has become the major problems.
G. Prasad   +3 more
semanticscholar   +1 more source

A FinFET‐Based Low‐Power Static Random Access Memory Cell With Improved Stability

International journal of numerical modelling
This work presents a FinFET‐based stable, and low‐power consuming static random access memory (SRAM) bit‐cell that used eight transistors. The performance parameter of proposed feedback‐cutting 8T (FC8T) is compared with four pre‐published cell circuits,
Gautam Rana   +3 more
semanticscholar   +1 more source

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