Results 231 to 240 of about 52,126 (300)

A 128Kb CMOS static random-access memory

IBM Journal of Research and Development, 1991
This paper describes an all-CMOS 128Kb static random-access memory (SRAM) with emitter-coupled-logic (ECL) I/O compatibility which was designed for the air-cooled Enterprise System/9000™ processors. Access time of 6.5 ns is achieved using 0.5-µm channel length and 1.0-µm minimum geometry. Pipelining and self-resetting circuit techniques permit the chip
J. L. Chu, H. R. Torabi, F. J. Towler
openaire   +1 more source

A multiple negative differential resistance heterojunction device and its circuit application to ternary static random access memory.

Nanoscale Horizons, 2020
For increasing the restricted bit-density in the conventional binary logic system, extensive research efforts have been directed toward implementing single devices with a two threshold voltage (VTH) characteristic via the single negative differential ...
Kwan-Ho Kim, Hyung‐Youl Park, J. Shim, Gicheol Shin, M. Andreev, Jiwan Koo, Gwangwe Yoo, Kilsu Jung, K. Heo, Yoonmyung Lee, Hyun‐Yong Yu, Kyung Rok Kim, J. Cho, Sungjoo Lee, Jin-Hong Park   +14 more
semanticscholar   +1 more source

Random testing of multi-port static random access memories

Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002), 2003
This paper presents the analysis and modeling of random testing for its application to multi-port memories. Ports operate to simultaneously test the memory and detecting multi-port related faults. The state of the memory under test in the presence of inter-port faults has been modeled using Markov state diagrams.
F. Karimi, F.J. Meyer, F. Lombardi
openaire   +1 more source

A static 4096-bit bipolar random-access memory

IEEE Journal of Solid-State Circuits, 1977
A description of a 23600 mil/SUP 2/, 35-ns 4096/spl times/1 bit bipolar RAM is presented. The historical evolution of density and performance of the 1024/spl times/1 forerunner along with advanced production and circuit techniques indicate the availability of an 11000 mil/SUP 2/, 10-ns, 4096/spl times/1 bipolar RAM by 1981.
W.H. Herndon, W. Ho, R. Ramirez
openaire   +1 more source

Low-power fast static random access memory cell

2010 International Conference on Computer Applications and Industrial Electronics, 2010
In this paper, we propose a new circuit-level technique to reduce the delay and power in SRAM cell during write operation. The proposed low-power fast (LPF) static random access memory (SRAM) cell contains two extra tail transistors in the respective inverter to avoid the charging or discharging of the bit-line.
C. M. R. Prabhu, Ajay Kumar Singh
openaire   +1 more source

A 256 bit Nonvolatile Static Random Access Memory with MNOS Memory Transistors

Japanese Journal of Applied Physics, 1975
A p-channel 256 bit nonvolatile static RAM which is essentially free from any limitation to the memory cycles is developed by means of a new concept of a nonvolatile flip-flop. The logical organization is 64 word × 4 bit. The memory can be operated as a static memory with access time of 400 ns and cycle time of 1 µs under a stable power supply, and as ...
S. Saito, N. Endo, Y. Uchida, T. Tanaka, Y. Nishi, K. Tamaru   +5 more
openaire   +1 more source

High‐Performance and Radiation‐Hard Carbon Nanotube Complementary Static Random‐Access Memory

Advanced Electronic Materials, 2019
Significant progress on carbon‐nanotube (CNT) electronics means that they are a serious candidate for use in high‐performance integrated circuits (ICs).
Maguang Zhu, Zhiyong Zhang, Lianmao Peng
semanticscholar   +1 more source

Static Random Access Memory Characteristics of Single-Gated Feedback Field-Effect Transistors

IEEE Transactions on Electron Devices, 2019
In this paper, we propose a novel static random access memory (SRAM) unit cell design and its array structure consisting of single-gated feedback field-effect transistors (FBFETs). To verify the SRAM characteristics, the basic memory operations and write
Jinsun Cho, Doohyeok Lim, Sola Woo, K. Cho, Sangsig Kim   +4 more
semanticscholar   +1 more source

Parallel programmable nonvolatile memory using ordinary static random access memory cells

Japanese Journal of Applied Physics, 2017
A technique of using an ordinary static random access memory (SRAM) array for a programmable nonvolatile (NV) memory is proposed. The parallel NV writing of the entire array is achieved by simply applying high-voltage stress to the power supply terminal, after storing inverted desired data in the static random access memory (SRAM) array.
Tomoko Mizutani, Kiyoshi Takeuchi, Takuya Saraya, Hirofumi Shinohara, Masaharu Kobayashi, Toshiro Hiramoto   +5 more
openaire   +1 more source

Differential Spin Hall Effect-Based Nonvolatile Static Random Access Memory for Energy-Efficient and Fast Data Restoration Application

IEEE transactions on magnetics, 2019
Spintronics, being a burgeoning area of research, aims to incorporate magnetic tunnel junction (MTJ), as a basic storage building block, to various electronic applications.
Sonal Shreya, Brajesh Kumar Kaushik
semanticscholar   +1 more source